Atmel AVR Assembler

AVR Assembler Help

Welcome to the ATMEL AVR Assembler.

  • What's New

  • Known Issues

Please select between the following Help items:

  • General information
  • Assembler source file composition
  • Instruction set overview
    • Arithmetic and Logic Instructions
    • Branch Instructions
    • Data Transfer Instructions
    • Bit and Bit-test Instructions
  • Assembler directives
  • Expressions
    • Expression operands
    • Expression operators
    • Functions in expressions
  • AVR Assembler 2 features

The Assembler is supplied as a WIN32 console program that can be used stand-alone or automatically invoked by AVR Studio. A description of how to use the Command line Assembler is included in this help file

Device specific instruction set summaries:

The actual instruction set varies between the devices. Use these links to verify the instruction set for the desired device.

  • AT90S1200
  • AT90S2313
  • AT90S2323 and AT90S2343
  • AT90S2333 and AT90S4433
  • AT90S4414 and AT90S8515
  • AT90S4434 and AT90S8535
  • AT90C8534
  • ATtiny11 and ATtiny12
  • ATtiny13/ATtiny2313
  • ATtiny25/ATtiny45/ATtiny85
  • ATtiny24/ATtiny44/ATtiny84
  • ATtiny261/ATtiny461/ATtiny861
  • ATtiny15
  • ATtiny22
  • ATtiny26
  • ATtiny261/461/861
  • ATtiny28
  • ATmega8 / ATmega48/88/168 / ATmega8515 / ATmega8535
  • ATmega16
  • ATmega161
  • ATmega162
  • ATmega163
  • ATmega169/165/329/325/3250/649/645
  • ATmega32
  • ATmega323
  • ATmega103
  • ATmega64/640/644, AT90CAN32/64
  • ATmega128/1280/1281 and AT90CAN128
  • ATmega406
  • ATmega2560/2561
  • AT90PWM2/3
  • ATxmega device family
  • AVR8L based tiny devices (ATtiny10)


What's New

What's New in this release

AVR Assembler 2.1.30 released with AVR Studio 4.15

  • Supports ATxmegaA3* and ATtiny10 devices

AVR Assembler 2.1.9 released with AVR Studio 4.12 Service Pack 3.

  • Minor enhancements and bug fixes. Click here for details.

AVR Asssembler 2.1.5 Released with AVR Studio 4.12 Service Pack 1.

  • This is a bugfix release only. Click here for details.

AVR Assembler 2.1 Released with AVR Studio 4.12 Sep-2005

  • AVRASM 2.1 is a major upgrade to AVRASM2, many preprocessor-assembler interaction problems and other bugs are fixed in this release.

  • XML Converter 2.21: Added support for converting new devices.

New AVR devices assembler support (include files)

Note that new devices are only supported by AVR Assembler 2.

Device | Include file
ATmega1281 | m1281def.inc
ATmega1280 | m1280def.inc
ATmega640 | m640def.inc
ATtiny261 | tn261def.inc
ATtiny461 | tn461def.inc
ATtiny861 | tn861def.inc
AT90CAN32 | can32def.inc
AT90CAN64 | can64def.inc
ATtiny44 | tn44def.inc
ATtiny84 | tn84def.inc

Previous releases

AVR Assembler 2.0 Released with AVR Studio 4.11 Jan-Mar 2005

  • AVRASM2 is now the default AVR Studio assembler. A lot of bugs are fixed, and some new features added, based on feedback from users testing the beta releases.

New include files and XML Converter.

  • A complete new set of include files are now available for AVRASM2. These should resolve most of the issues experienced during the AVRASM2 beta period.

  • The XML converter program used to machine-generate the new include files is included in this release. In addition to generating assembler include files, this program can be used to produce header files for AVR-GCC, and header and linker files for the IAR C compiler.

AVR Assembler v1.77.3 date Mar-2005

  • The old assembler and include files are still included in this AVR Studio release. It may be selected in Studio for use with existing projects, but is now unsupported and support for new devices will not be added. This will be the last AVRASM1 version.

New AVR devices support

  • ATmega2561 / ATmega2560

  • AT90PWM2 / AT90PWM3

  • ATtiny25/45/85

  • ATmega406

AVR Assembler v1.77.1 date Oct-2004

  • Added device directives for ATtiny25/45/85, AT90PWM2/3, ATmega325/645

AVR Assembler 2 Beta date Jun-2004

  • A new AVR assembler version with many new features: AVR Assembler 2

AVR Assembler v1.76 date May-2004

  • Included device directive for ATmega165.

  • Detect and report incorrect use of conditionals on forward referenced labels, causing incorrect offset calculations for relative branches.

  • Instruction set issues for some parts fixed.

  • Assembler recognizes '#' as comments (same as ';'), to cause it ignore AVRASM2 preprocessor directives.

AVR Assembler v1.75 date Mar-2004

  • Included device directives for ATmega88, ATmega168, ATmega329 and AT90CAN128.

  • DSEG directive is now correct for devices with extended IO

  • Wrap relative jumps. For devices with more than 4k words of program memory, using this option may cause unpredictable results and it should be turned off. If it is left on, the assembler will now produce a warning.

  • Assembler now warns about operand combinations that cause undefined behaviour, like 'ld r30,z+'

  • Assembler now supports extended ASCII characters in character constants and strings.

  • Undetected syntax errors in .db directive fixed

AVR Assembler v1.74 date dec-2003

  • New conditional assembly directives. Please notice that the directive are changed from # to . from the beta version.

    .ifdef <symbol>
    .ifndef <symbol>
    .if <expression>
    .elif <expression>
    .else
    .endif

    More details here..

  • Output directives
    .message "str"
    .error "str"

  • Fixed bug in .hex file generation. Example: When trying to place code on 0x07FFF using .org the content was placed on 0xFFFE instead. This is fixed now.

  • included device directives for ATtiny2313 and ATmega48.

AVR Assembler v1.60 date 24-jun-2003

  • Included device directive for ATtiny13.

AVR Assembler v1.56 date 30-apr-2002

  • Included device directives for ATmega162, ATmega169, ATmega8515, ATmega8535, ATtiny26, AT86RF401.

  • Added *.def.inc files for the above mentioned devices.


Atmel AVR Assembler - Source

Assembler source

The Assembler works on source files containing instruction mnemonics, labels and directives. The instruction mnemonics and the directives often take operands.

Code lines should be limited to 120 characters.

Every input line can be preceded by a label, which is an alphanumeric string terminated by a colon. Labels are used as targets for jump and branch instructions and as variable names in Program memory and RAM.

An input line may take one of the four following forms:

[label:] directive [operands] [Comment]
[label:] instruction [operands] [Comment]
Comment
Empty line
A comment has the following form:
; [Text]
Items placed in braces are optional. The text between the comment-delimiter (;) and the end of line (EOL) is ignored by the Assembler. Labels, instructions and directives are described in more detail later.

If you use AVR Assembler 2 (AVRASM2) you should also read AVR Assembler 2 Syntax.

Examples:

label:   .EQU var1=100 ; Set var1 to 100 (Directive)
         .EQU var2=200 ; Set var2 to 200                                                               test:    rjmp test     ; Infinite loop (Instruction)
                       ; Pure comment line                                                                                   ; Another comment line
Note that there are no restrictions with respect to column placement of labels, directives, comments or instructions.


Atmel AVR Assembler - General

General information

The Assembler translates assembly source code into object code. The generated object code can be used as input to a simulator such as the ATMEL AVR Simulator or an emulator such as the ATMEL AVR In-Circuit Emulator. The Assembler also generates a PROMable hex code which can be programmed directly into the program memory of an AVR microcontroller

The Assembler generates fixed code allocations, consequently no linking is necessary.

The instruction set of the AVR family of microcontrollers is only briefly described, refer to the AVR Data Book in order to get more detailed knowledge of the instruction set for the different microcontrollers.


Atmel AVR Assembler - Instructions

Instruction mnemonics

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
EIJMP | None | Extended Indirect Jump (Z) | STACK = PC+1, PC(15:0) = Z, PC(21:16) = EIND | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
EICALL | None | Extended Indirect Call to (Z) | STACK = PC+1, PC(15:0) = Z, PC(21:16) =EIND | None | 4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2
* Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses through the external RAM interface. For the instructions CALL, ICALL, EICALL, RCALL, RET and RETI, add three cycles plus two cycles for each wait state in devices with up to 16 bit PC (128KB program memory). For devices with more than 128KB program memory, add five cycles plus three cycles for each wait state.

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
ELPM | None | Extended Load Program Memory | R0 = (RAMPZ:Z) | None | 3
ELPM | Rd,Z | Extended Load Program Memory | Rd = (RAMPZ:Z) | None | 3
ELPM | Rd,Z+ | Extended Load Program Memory and Post Increment | Rd = (RAMPZ:Z), Z = Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
ESPM | None | Extended Store Program Memory | (RAMPZ:Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2
* Cycle times for data memory accesses assume internal memory accesses and are not valid for accesses through the external RAM interface. For the LD, ST, LDD, STD, LDS, STS, PUSH and POP instructions, add one cycle plus one cycle for each wait state.

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


Atmel AVR Assembler - Directives

Assembler directives

The Assembler supports a number of directives. The directives are not translated directly into opcodes. Instead, they are used to adjust the location of the program in memory, define macros, initialize memory and so on. An overview of the directives is given in the following table.
Directive | Description
BYTE | Reserve byte to a variable
CSEG | Code Segment
CSEGSIZE | Program memory size
DB | Define constant byte(s)
DEF | Define a symbolic name on a register
DEVICE | Define which device to assemble for
DSEG | Data Segment
DW | Define Constant word(s)
ENDM, ENDMACRO | EndMacro
EQU | Set a symbol equal to an expression
ESEG | EEPROM Segment
EXIT | Exit from file
INCLUDE | Read source from another file
LIST | Turn listfile generation on
LISTMAC | Turn Macro expansion in list file on
MACRO | Begin Macro
NOLIST | Turn listfile generation off
ORG | Set program origin
SET | Set a symbol to an expression

These directives were introduced in AVRASM v1.74:
New Directives | Description
ELSE,ELIF | Conditional assembly
ENDIF | Conditional assembly
ERROR | Outputs an error message
IF,IFDEF,IFNDEF | Conditional assembly
MESSAGE | Outputs a message string

The following directives are only available with AVRASM2:

AVRASM2 Directives | Description
DD | Define Doubleword
DQ | Define Quadword
UNDEF | Undefine register symbol
WARNING | Outputs a warning message
OVERLAP/NOOVERLAP | Set up overlapping section (requires AVRASM2.1 or better)

Note that all directives must be preceded by a period.

BYTE - Reserve bytes to a variable

The BYTE directive reserves memory resources in the SRAM or EEPROM. In order to be able to refer to the reserved location, the BYTE directive should be preceded by a label. The directive takes one parameter, which is the number of bytes to reserve. The directive can not be used within a Code segment (see directives CSEG, DSEG, and ESEG). Note that a parameter must be given. The allocated bytes are not initialized.

Syntax:
LABEL: .BYTE expression

Example:
.DSEG
var1:    .BYTE 1            ; reserve 1 byte to var1
table:   .BYTE tab_size     ; reserve tab_size bytes

.CSEG
         ldi r30,low(var1)  ; Load Z register low
         ldi r31,high(var1) ; Load Z register high
         ld r1,Z            ; Load VAR1 into register 1

CSEG - Code segment

The CSEG directive defines the start of a Code Segment. An Assembler file can consist of several Code Segments, which are concatenated into one Code Segment when assembled. The BYTE directive can not be used within a Code Segment. The default segment type is Code. The Code Segments have their own location counter which is a word counter. The ORG directive can be used to place code and constants at specific locations in the Program memory. The directive does not take any parameters.

Syntax:
.CSEG

Example:
.DSEG                       ; Start data segment
vartab: .BYTE 4             ; Reserve 4 bytes in SRAM

.CSEG                       ; Start code segment
const:  .DW 2               ; Write 0x0002 in prog.mem.
        mov r1,r0           ; Do something

CSEGSIZE - Program Memory Size

AT94K devices have a user configurable memory partition between the AVR Program memory and the data memory. The program and data SRAM is divided into three blocks: 10K x 16 dedicated program SRAM, 4K x 8 dedicated data SRAM, and 6K x 16 or 12K x 8 configurable SRAM which may be swapped between program and data memory spaces in 2K x 16 or 4K x 8 partitions.
This directive is used to specify the size of the program memory block.

Syntax:
.CSEGSIZE = 10 | 12 | 14 | 16

Example:
.CSEGSIZE = 12              ; Specifies the program meory size as 12K x 16

DB - Define constant byte(s) in program memory and EEPROM

The DB directive reserves memory resources in the program memory or the EEPROM memory. In order to be able to refer to the reserved locations, the DB directive should be preceded by a label. The DB directive takes a list of expressions, and must contain at least one expression. The DB directive must be placed in a Code Segment or an EEPROM Segment.

The expression list is a sequence of expressions, delimited by commas. Each expression must evaluate to a number between -128 and 255. If the expression evaluates to a negative number, the 8 bits twos complement of the number will be placed in the program memory or EEPROM memory location.

If the DB directive is given in a Code Segment and the expressionlist contains more than one expression, the expressions are packed so that two bytes are placed in each program memory word. If the expressionlist contains an odd number of expressions, the last expression will be placed in a program memory word of its own, even if the next line in the assemby code contains a DB directive. The unused half of the program word is set to zero. A warning is given, in order to notify the user that an extra zero byte is added to the .DB statement

Syntax:
LABEL:  .DB expressionlist

Example:
.CSEG
consts: .DB 0, 255, 0b01010101, -128, 0xaa

.ESEG
const2: .DB 1,2,3

DEF - Set a symbolic name on a register

The DEF directive allows the registers to be referred to through symbols. A defined symbol can be used in the rest of the program to refer to the register it is assigned to. A register can have several symbolic names attached to it. A symbol can be redefined later in the program.

Syntax:
.DEF Symbol=Register

Example:
.DEF temp=R16
.DEF ior=R0

.CSEG
 ldi temp,0xf0  ; Load 0xf0 into temp register
 in ior,0x3f  ; Read SREG into ior register
 eor temp,ior  ; Exclusive or temp and ior

UNDEF - Undefine a register symbolic name

This directive is only available with AVRASM2.

'The UNDEF directive is used to undefine a symbol previously defined with the DEF directive. This provides a way to obtain a simple scoping of register definitions, to avoid warnings about register reuse.

Syntax:
.UNDEF symbol

E xample:
.DEF var1 = R16
ldi var1, 0x20
... ; do something more with var1
.UNDEF var1

.DEF var2 = R16 ; R16 can now be reused without warning.

DEVICE - Define which device to assemble for (deprecated)

Note: The .DEVICE directive is deprecated and should no longer be used with AVRASM2. It is replaced with a number of #pragma directives, describing the device properties. In AVRASM2, .device is roughly equivalent to #pragma AVRPART PART_NAME, but the device name may be anything and is not limited to the table below. Also, only the device name is set by .device, the other device properties must be set separately. The description and table below is only valid for AVRASM 1.x, ant the table is not updated with new devices.

The DEVICE directive allows the user to tell the Assembler which device the code is to be executed on. Using this directive, a warning is issued if an instruction not supported by the specified device occurs. If the Code Segment or EEPROM Segment are larger than supplied by the device, a warning message is given. If the directive is not used, it is assumed that all instructions are supported and that there are no restrictions on Program and EEPROM memory.

Syntax:
.DEVICE <device code>

Table: Device codes for devices supported by AVRASM 1.x:

Classic | Tiny | Mega | Other
AT90S120 | ATtiny11 | ATmega8 | AT94K
AT90S4433 | ATtiny2313 | ATmega48 | AT86RF401
AT90S2313 | ATtiny12 | ATmega16 | AT90CAN128
AT90S2323 | ATtiny13 | ATmega161 |
AT90S2333 | ATtiny22 | ATmega162 |
AT90S4414 | ATtiny26 | ATmega163 |
AT90S4434 | ATtiny25 | ATmega169 |
AT90S8515 | ATtiny45 | ATmega32 |
AT90S8534 | ATtiny85 | ATmega323 |
AT90S8535 |  | ATmega103 |
AT90S2343 |  | ATmega104 |
 |  | ATmega8515 |
 |  | ATmega8535 |
 |  | ATmega64 |
 |  | ATmega128 |
 |  | ATmega165 |
 |  | ATmega2560 |
 |  | ATmega2561 |

Example:
.DEVICE AT90S1200  ; Use the AT90S1200

.CSEG
        push r30   ; This statement will generate a warning
                   ; since the specified device does not
                   ; have this instruction

Note: There has been a change of names that took effect 14.06.2001. The following devices are affected:

Old name            New name

ATmega104           ATmega128

ATmega32            ATmega323

ATmega164           ATmega16

In order NOT to break old projects, both old and new device directives are allowed for the parts that are affected.

DSEG - Data Segment

The DSEG directive defines the start of a Data segment. An assembler source file can consist of several data segments, which are concatenated into a single data segment when assembled. A data segment will normally only consist of BYTE directives (and labels). The Data Segments have their own location counter which is a byte counter. The ORG directive can be used to place the variables at specific locations in the SRAM. The directive does not take any parameters.

Syntax:
.DSEG

Example:
.DSEG                        ; Start data segment
var1:  .BYTE 1               ; reserve 1 byte to var1
table:  .BYTE tab_size       ; reserve tab_size bytes.

.CSEG
        ldi r30,low(var1)    ; Load Z register low
        ldi r31,high(var1)   ; Load Z register high
        ld r1,Z              ; Load var1 into register 1

DW - Define constant word(s) in program memory and EEPROM

The DW directive reserves memory resources in the program memory or the EEPROM memory. In order to be able to refer to the reserved locations, the DW directive should be preceded by a label.
The DW directive takes a list of expressions, and must contain at least one expression.
The DB directive must be placed in a Code Segment or an EEPROM Segment.

The expression list is a sequence of expressions, delimited by commas. Each expression must evaluate to a number between -32768 and 65535. If the expression evaluates to a negative number, the 16 bits two's complement of the number will be placed in the program memory or EEPROM memory location.

Syntax:
LABEL: .DW expressionlist

Example:
.CSEG
varlist:  .DW 0, 0xffff, 0b1001110001010101, -32768, 65535

.ESEG
eevarlst: .DW 0,0xffff,10

DD - Define constant doubleword(s) in program memory and EEPROM
DQ - Define constant quadword(s) in program memory and EEPROM

These directives are only available with AVRASM2.

These directives are very similar to the .DW directive, except they are used to define 32-bit (doubleword) and 64-bit (quadword) respectively. The data layout in memory is strictly little-endian.

Syntax:
LABEL: .DD expressionlist
LABEL: .DQ expressionlist

Example:
.CSEG
varlist:  .DD 0, 0xfadebabe, -2147483648, 1 << 30

.ESEG
eevarlst: .DQ 0,0xfadebabedeadbeef, 1 << 62

ELIF,ELSE - conditional assembly

.ELIF will include code until the corresponding ENDIF of the next ELIF at the same level if the expression is true, and both the initial .IF clause and all following .ELIF clauses are false.

.ELSE will include code until the corresponding .ENDIF if the initial.IF clause and all .ELIF clauses (if any) all are false.

Syntax:
.ELIF<expression>
.ELSE

.IFDEF <symbol> |.IFNDEF <symbol>
...
.ELSE | .ELIF<expression>
...
.ENDIF

Example:
.IFDEF DEBUG
.MESSAGE "Debugging.."
.ELSE
.MESSAGE "Release.."
.ENDIF

ENDIF - conditional assembly

Conditional assembly includes a set of commands at assembly time. The ENDIF directive defines the end for the conditional IF or IFDEF or IFNDEF directives.

Conditionals (.IF...ELIF...ELSE...ENDIF blocks) may be nested, but all conditionals must be terminated at the end of file (conditionals may not span multiple files).

Syntax:
.ENDIF

.IFDEF <symbol> |.IFNDEF <symbol>
...
.ELSE | .ELIF<expression>
...
.ENDIF

Example:
.IFNDEF DEBUG
.MESSAGE "Release.."
.ELSE
.MESSAGE "Debugging.."
.ENDIF

ENDM, ENDMACRO - End macro

The ENDMACRO directive defines the end of a macro definition. The directive does not take any parameters. See the MACRO directive for more information on defining macros. ENDM is an alternative form, fully equivalent with ENDMACRO.

Syntax:
.ENDMACRO
.ENDM

Example:
.MACRO SUBI16               ; Start macro definition
        subi r16,low(@0)    ; Subtract low byte
        sbci r17,high(@0)   ; Subtract high byte
.ENDMACRO

EQU - Set a symbol equal to an expression

The EQU directive assigns a value to a label. This label can then be used in later expressions. A label assigned to a value by the EQU directive is a constant and can not be changed or redefined.

Syntax:
.EQU label = expression

Example:
.EQU io_offset = 0x23
.EQU porta     = io_offset + 2

.CSEG                 ; Start code segment
        clr r2        ; Clear register 2
        out porta,r2  ; Write to Port A

ERROR - Outputs an error message string

The ERROR directive outputs a string and halts the assembling. May be used in conditional assembly.

Syntax:
.ERROR "<string>"

Example:
.IFDEF TOBEDONE
.ERROR "Still stuff to be done.."
.ENDIF

WARNING - Outputs a warning message string

The .WARNING directive outputs a warning string, but unlike the .ERROR directive does not halt assembling. May be used in conditional assembly.

Syntax:
.WARNING"<string>"

Example:
.IFDEF EXPERIMENTAL_FEATURE
.WARNING "This is not properly tested, use at own risk."
.ENDIF

ESEG - EEPROM Segment

The ESEG directive defines the start of an EEPROM segment. An assembler source file can consist of several EEPROM segments, which are concatenated into a single EEPROM segment when assembled. An EEPROM segment will normally only consist of DB and DW directives (and labels). The EEPROM segments have their own location counter which is a byte counter. The ORG directive can be used to place the variables at specific locations in the EEPROM. The directive does not take any parameters.

Syntax:
.ESEG

Example:
.DSEG                    ; Start data segment
var1:   .BYTE 1          ; reserve 1 byte to var1
table:  .BYTE tab_size   ; reserve tab_size bytes.

.ESEG
eevar1: .DW 0xffff        ; initialize 1 word in EEPROM

EXIT - Exit this file

The EXIT directive tells the Assembler to stop assembling the file. Normally, the Assembler runs until end of file (EOF). If an EXIT directive appears in an included file, the Assembler continues from the line following the INCLUDE directive in the file containing the INCLUDE directive.

Syntax:
.EXIT

Example:
.EXIT  ; Exit this file

INCLUDE - Include another file

The INCLUDE directive tells the Assembler to start reading from a specified file. The Assembler then assembles the specified file until end of file (EOF) or an EXIT directive is encountered. An included file may itself contain INCLUDE directives.

Syntax:
.INCLUDE "filename"

Example:
; iodefs.asm:
.EQU sreg   = 0x3f     ; Status register
.EQU sphigh = 0x3e     ; Stack pointer high
.EQU splow  = 0x3d     ; Stack pointer low

; incdemo.asm
.INCLUDE iodefs.asm    ; Include I/O definitions
        in r0,sreg     ; Read status register

IF,IFDEF,IFNDEF - conditional assembly

Conditional assembly includes a set of commands at assembly time. The IFDEF directive will include code till the corresponding ELSE directive if <symbol> is defined. The symbol must be defined with the EQU or SET directive. (Will not work with the DEF directive) The IF directive will include code if <expression> is evaluated different from 0. Valid till the corresponding ELSE or ENDIF directive.

Up to 5 levels of nesting is possible.

Syntax:
.IFDEF <symbol>
.IFNDEF <symbol>
.IF <expression>

.IFDEF <symbol> |.IFNDEF <symbol>
...
.ELSE | .ELIF<expression>
...
.ENDIF

Example:
.MACRO SET_BAT
.IF @0>0x3F
.MESSAGE "Address larger than 0x3f"
lds @2, @0
sbr @2, (1<<@1)
sts @0, @2
.ELSE
.MESSAGE "Address less or equal 0x3f"
.ENDIF
.ENDMACRO

LIST - Turn the listfile generation on

The LIST directive tells the Assembler to turn listfile generation on. The Assembler generates a listfile which is a combination of assembly source code, addresses and opcodes. Listfile generation is turned on by default. The directive can also be used together with the NOLIST directive in order to only generate listfile of selected parts of an assembly source file.

Syntax:
.LIST

Example:
.NOLIST                ; Disable listfile generation
.INCLUDE "macro.inc"   ; The included files will not
.INCLUDE "const.def"   ; be shown in the listfile
.LIST                  ; Reenable listfile generation

LISTMAC - Turn macro expansion on

The LISTMAC directive tells the Assembler that when a macro is called, the expansion of the macro is to be shown on the listfile generated by the Assembler. The default is that only the macro-call with parameters is shown in the listfile.

Syntax:
.LISTMAC

Example:
.MACRO MACX         ; Define an example macro
        add  r0,@0  ; Do something
        eor  r1,@1  ; Do something
.ENDMACRO           ; End macro definition

.LISTMAC            ; Enable macro expansion
        MACX r2,r1  ; Call macro, show expansion

MACRO - Begin macro

The MACRO directive tells the Assembler that this is the start of a Macro. The MACRO directive takes the Macro name as parameter. When the name of the Macro is written later in the program, the Macro definition is expanded at the place it was used. A Macro can take up to 10 parameters. These parameters are referred to as @0-@9 within the Macro definition. When issuing a Macro call, the parameters are given as a comma separated list. The Macro definition is terminated by an ENDMACRO directive.

By default, only the call to the Macro is shown on the listfile generated by the Assembler. In order to include the macro expansion in the listfile, a LISTMAC directive must be used. A macro is marked with a + in the opcode field of the listfile.

Syntax:
.MACRO macroname

Example:
.MACRO SUBI16                   ; Start macro definition
        subi @1,low(@0)         ; Subtract low byte
        sbci @2,high(@0)        ; Subtract high byte
.ENDMACRO                       ; End macro definition

.CSEG                           ; Start code segment
        SUBI16 0x1234,r16,r17   ; Sub.0x1234 from r17:r16

MESSAGE - Output a message string

The MESSAGE directive outputs a string. Useful in conditional assembly.

Syntax:
.MESSAGE "<string>"

Example:
.IFDEF DEBUG
.MESSAGE "Debug mode"
.ENDIF

NOLIST - Turn listfile generation off

The NOLIST directive tells the Assembler to turn listfile generation off. The Assembler normally generates a listfile which is a combination of assembly source code, addresses and opcodes. Listfile generation is turned on by default, but can be disabled by using this directive. The directive can also be used together with the LIST directive in order to only generate listfile of selected parts of an assembly source file.

Syntax:
.NOLIST

Example:
.NOLIST                 ; Disable listfile generation
.INCLUDE "macro.inc"    ; The included files will not
.INCLUDE "const.def"    ; be shown in the listfile
.LIST                   ; Reenable listfile generation

ORG - Set program origin

The ORG directive sets the location counter to an absolute value. The value to set is given as a parameter. If an ORG directive is given within a Data Segment, then it is the SRAM location counter which is set, if the directive is given within a Code Segment, then it is the Program memory counter which is set and if the directive is given within an EEPROM Segment, it is the EEPROM location counter which is set.

The default values of the Code and the EEPROM location counters are zero, and the default value of the SRAM location counter is the address immediately following the end of I/O address space (0x60 for devices without extended I/O, 0x100 or more for devices with extended I/O) when the assembling is started. Note that the SRAM and EEPROM location counters count bytes whereas the Program memory location counter counts words. Also note that some devices lack SRAM and/or EEPROM.

Syntax:
.ORG expression

Example:
.DSEG                ; Start data segment

.ORG 0x120           ; Set SRAM address to hex 120
variable: .BYTE 1    ; Reserve a byte at SRAM adr. 0x120

.CSEG
.ORG 0x10            ; Set Program Counter to hex 10
          mov r0,r1  ; Do something

SET - Set a symbol equal to an expression

The SET directive assigns a value to a label. This label can then be used in later expressions. Unlike the .EQU directive, a label assigned to a value by the SET directive can be changed (redefined) later in the program.

Syntax:
.SET label = expression

Example:
.SET FOO = 0x114       ; set FOO to point to an SRAM location
        lds r0, FOO  ; load location into r0
.SET FOO = FOO + 1     ; increment (redefine) FOO. This would be illegal if using .EQU
        lds r1, FOO  ; load next location into r1

OVERLAP/NOOVERLAP - Set up overlapping section

Introduced in AVRASM 2.1. These directives are for projects with special needs and should normally not be used.

These directives only affect the currently active segment (cseg/dseg/eseg).

The .overlap/nooverlap directives mark a section that will be allowed to overlap code/data with code/data defined elsewhere, without any error or warning messages being generated. This is totally independent of what is set using the #pragma overlap directives. The overlap-allowed attribute will stay in effect across .org directives, but will not follow across .cseg/.eseg/.dseg directives (each segment marked separately).

Syntax:
.OVERLAP
.NOOVERLAP

Example:
.overlap
.org 0                   ; section #1
    rjmp    default
.nooverlap

.org 0                   ; section #2
    rjmp    RESET        ; No error given here
.org 0                   ; section #3
    rjmp    RESET        ; Error here because overlap with #2

The typical use of this is to set up some form of default code or data that may or may not later be modified by overlapping code or data, without having to disable assembler overlap detection altogether.


Atmel AVR Assembler - Expressions

Expressions

The Assembler incorporates constant expressions. Expressions can consist of operands, operators and functions. All expressions are internally 32 bits in AVRASM, and 64 bits in AVRASM2.

Operands

The following operands can be used:
  • User defined labels which are given the value of the location counter at the place they appear.
  • User defined variables defined by the SET directive
  • User defined constants defined by the EQU directive
  • Integer constants: constants can be given in several formats, including
    • Decimal (default): 10, 255
    • Hexadecimal (two notations): 0x0a, $0a, 0xff, $ff
    • Binary: 0b00001010, 0b11111111
    • Octal (leading zero): 010, 077
  • PC - the current value of the Program memory location counter
  • Floating point constants - AVRASM2 only.

Operators

The Assembler supports a number of operators which are described here. The higher the precedence, the higher the priority. Expressions may be enclosed in parentheses, and such expressions are always evaluated before combined with anything outside the parentheses. The associativity of binary operators indicates the evaluation order of chained operators, left associativity meaning they are evaluated left to right, i.e., 2 - 3 - 4 is (2 - 3) - 4, while right associativity would mean 2-3-4 is 2 - (3 - 4). Some operators are not assoiciative, meaning chaining has no meaning.

The following operators are defined:

Symbol | Description
! | Logical Not
~ | Bitwise Not
- | Unary Minus
* | Multiplication
/ | Division
% | Modulo (AVRASM2 only)
+ | Addition
- | Subtraction
<< | Shift left
>> | Shift right
< | Less than
<= | Less than or equal
> | Greater than
>= | Greater than or equal
== | Equal
!= | Not equal
& | Bitwise And
^ | Bitwise Xor
| | Bitwise Or
&& | Logical And
|| | Logical Or
? | Conditional operator (AVRASM2 only)

Logical Not

Symbol:        !
Description:   Unary operator which returns 1 if the expression was zero, and returns 0 if the expression was nonzero
Precedence:    12
Associativity: None
Example:       ldi r16,!0xf0  ; Load r16 with 0x00

Bitwise Not

Symbol:        ~
Description:   Unary operator which returns the input expression with all bits inverted
Precedence:    12
Associativity: None
Example:       ldi r16,~0xf0  ; Load r16 with 0x0f

Unary Minus

Symbol:        -
Description:   Unary operator which returns the arithmetic negation of an expression
Precedence:    14
Associativity: None
Example:       ldi r16,-2  ; Load -2(0xfe) in r16

Multiplication

Symbol:        *
Description:   Binary operator which returns the product of two expressions
Precedence:    13
Associativity: Left
Example:       ldi r30,label*2 ; Load r30 with label*2

Division

Symbol:        /
Description:   Binary operator which returns the integer quotient of the left expression divided by the right expression
Precedence:    13
Associativity: Left
Example:       ldi r30,label/2 ; Load r30 with label/2

Modulo (AVRASM2 Only)

Symbol:        %
Description:   Binary operator which returns the integer remainder of the left expression divided by the right expression
Precedence:    13
Associativity: Left
Example:       ldi r30,label%2 ; Load r30 with label%2

Addition

Symbol:        +
Description:   Binary operator which returns the sum of two expressions
Precedence:    12
Associativity: Left
Example:       ldi r30,c1+c2  ; Load r30 with c1+c2

Subtraction

Symbol:        -
Description:   Binary operator which returns the left expression minus the right expression
Precedence:    12
Associativity: Left
Example:       ldi r17,c1-c2  ;Load r17 with c1-c2

Shift left

Symbol:        <<
Description:   Binary operator which returns the left expression shifted left the number given by the right expression
Precedence:    11
Associativity: Left
Example:       ldi r17,1<<bitmask  ;Load r17 with 1 shifted left bitmask times

Shift right

Symbol:        >>
Description:   Binary operator which returns the left expression shifted right the number given by the right expression
Precedence:    11
Associativity: Left
Example:       ldi r17,c1>>c2  ;Load r17 with c1 shifted right c2 times

Less than

Symbol:        <
Description:   Binary operator which returns 1 if the signed expression to the left is Less than the signed expression to the right, 0 otherwise
Precedence:    10
Associativity: None
Example:       ori r18,bitmask*(c1<c2)+1  ;Or r18 with an expression

Less or equal

Symbol:        <=
Description:   Binary operator which returns 1 if the signed expression to the left is Less than or Equal to the signed expression to the right, 0 otherwise
Precedence:    10
Associativity: None
Example:       ori r18,bitmask*(c1<=c2)+1 ;Or r18 with an expression

Greater than

Symbol:        >
Description:   Binary operator which returns 1 if the signed expression to the left is Greater than the signed expression to the right, 0 otherwise
Precedence:    10
Associativity: None
Example:       ori r18,bitmask*(c1>c2)+1  ;Or r18 with an expression

Greater or equal

Symbol:        >=
Description:   Binary operator which returns 1 if the signed expression to the left is Greater than or Equal to the signed expression to the right, 0 otherwise
Precedence:    10
Associativity: None
Example:       ori r18,bitmask*(c1>=c2)+1 ;Or r18 with an expression

Equal

Symbol:        ==
Description:   Binary operator which returns 1 if the signed expression to the left is Equal to the signed expression to the right, 0 otherwise
Precedence:    9
Associativity: None
Example:       andi r19,bitmask*(c1==c2)+1 ;And r19 with an expression

Not equal

Symbol:        !=
Description:   Binary operator which returns 1 if the signed expression to the left is Not Equal to the signed expression to the right, 0 otherwise
Precedence:    9
Associativity: None
Example:       .SET flag=(c1!=c2)  ;Set flag to 1 or 0

Bitwise And

Symbol:        &
Description:   Binary operator which returns the bitwise And between two expressions
Precedence:    8
Associativity: Left
Example:       ldi r18,High(c1&c2) ;Load r18 with an expression

Bitwise Xor

Symbol:        ^
Description:   Binary operator which returns the bitwise Exclusive Or between two expressions
Precedence:    7
Associativity: Left
Example:       ldi r18,Low(c1^c2) ;Load r18 with an expression

Bitwise Or

Symbol:        |
Description:   Binary operator which returns the bitwise Or between two expressions
Precedence:    6
Associativity: Left
Example:       ldi r18,Low(c1|c2) ;Load r18 with an expression

Logical And

Symbol:        &&
Description:   Binary operator which returns 1 if the expressions are both nonzero, 0 otherwise
Precedence:    5
Associativity: Left
Example:       ldi r18,Low(c1&&c2)  ;Load r18 with an expression

Logical Or

Symbol:        ||
Description:   Binary operator which returns 1 if one or both of the expressions are nonzero, 0 otherwise
Precedence:    4
Associativity: Left
Example:       ldi r18,Low(c1||c2)  ;Load r18 with an expression

Conditional operator (AVRASM2 only)

Symbol:        ? :
Syntax:        condtion? expression1 : expression2
Description:   Ternary operator which returns expression1 if condition is true, expression2 otherwise.
Precedence:    3
Associativity: None
Example:       ldi r18, a > b? a : b  ; Load r18 with the maximum numeric value of a and b.
Note:          This feature was introduced in AVRASM 2.1 and is not available in 2.0 or earlier versions.

Functions

The following functions are defined:
  • LOW(expression) returns the low byte of an expression
  • HIGH(expression) returns the second byte of an expression
  • BYTE2(expression) is the same function as HIGH
  • BYTE3(expression) returns the third byte of an expression
  • BYTE4(expression) returns the fourth byte of an expression
  • LWRD(expression) returns bits 0-15 of an expression
  • HWRD(expression) returns bits 16-31 of an expression
  • PAGE(expression) returns bits 16-21 of an expression
  • EXP2(expression) returns 2 to the power of expression
  • LOG2(expression) returns the integer part of log2(expression)
The following functions are only defined in AVRASM2:
  • INT(expression) Truncates a floating point expression to integer (ie discards fractional part)
  • FRAC(expression) Extracts fractional part of a floating point expression (ie discards integer part).
  • Q7(expression) Converts a fractional floating point expression to a form suitable for the FMUL/FMULS/FMULSU instructions. (sign + 7-bit fraction)
  • Q15(expression) Converts a fractional floating point expression to a form suitable for the FMUL/FMULS/FMULSU instructions. (sign +15-bit fraction)
  • ABS() Returns the absolute value of a constant expression.
  • DEFINED(symbol) Returns true if symbol is previously defined using .equ/.set/.def directives. Normally used in conjunction with .if directives (.if defined(foo)), but may be used in any context. It differs from other functions in that parentheses around its argument are not required, and that it only makes sense to use a single symbol as argument.
  • STRLEN(string) returns the length of a string c+onstant, in bytes.


AT90S1200 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


AT90S2323 and AT90S2343 Instruction Set

AT90S2323 and AT90S2343 Instruction Set Summary

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct from Data Space | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


AT90S4414 and AT90S8515 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


AT90S4434 and AT90S8535 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega8 / ATmega48/88/168 / ATmega8515 / ATmega8535 Instruction Set

ATmega8 / ATmega48/88/168 / ATmega8515 / ATmega8535 / AT90PWM2/3 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP (Note 1) | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL (Note 1) | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
STD | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
STD | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLS | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

NOTE 1: These instructions are only available in ATmega168.

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega103 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
ELPM (Note 1) | None | Extended Load Program Memory | R0 = (RAMPZ:Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Note 1: Not supported in ATmega603

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega16/32 Instruction Set

ATmega16/32, ATmega406 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega161 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega162 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega163 Instruction Set

ATmega163 and ATmega323 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega169/ATmega165 Instruction Set

ATmega169/165/329/325/3250/649/645 [P] Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega64/644/640, AT90CAN32/64 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega128/1280/1281 and AT90CAN128 Instruction Set

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
ELPM | None | Extended Load Program Memory | R0 = (RAMPZ:Z) | None | 3
ELPM | Rd,Z | Extended Load Program Memory | Rd = (RAMPZ:Z) | None | 3
ELPM | Rd,Z+ | Extended Load Program Memory and Post-Increment | Rd = (RAMPZ:Z), Z = Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATmega256 Instruction Set

ATmega2560/2561 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
EIJMP | None | Extended Indirect Jump (Z) | PC(15:0) = Z, PC(21:16) = EIND | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
EICALL | None | Extended Indirect Call (Z) | STACK = PC+1, PC(15:0) = Z, PC(21:16) = EIND | None | 4
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
ELPM | None | Extended Load Program Memory | R0 = (RAMPZ:Z) | None | 3
ELPM | Rd,Z | Extended Load Program Memory | Rd = (RAMPZ:Z) | None | 3
ELPM | Rd,Z+ | Extended Load Program Memory and Post-Increment | Rd = (RAMPZ:Z), Z = Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny11/12 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2*
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny13/ATtiny2313 Instruction Set

ATtiny13, ATtiny2313, ATtiny25/45/85, ATtiny24/44/84, ATtiny261/461/861 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
SPM | None | Store Program Memory | (Z) = R1:R0 | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny15 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2*
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny22 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny26 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny28 Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
ST | Z,Rr | Store Indirect | (Z)= Rr | None | 2*
LPM | None | Load Program Memory | R0 = (Z) | None | 3
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATxmega Instruction Set

The Assembler accepts mnemonic instructions from the instruction set. A summary of the instruction set mnemonics and their parameters is given here. For a detailed description of the Instruction set, refer to the AVR Data Book.

This instruction set is common to all ATxmega devices, with exceptions as noted below.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
ADIW | Rd, K | Add Immediate To Word | Rd+1:Rd,K | Z,C,N,V,S | 2
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1
SBIW | Rdl,K6 | Subtract Immediate from Word | Rdh:Rdl = Rdh:Rdl - K 6 | Z,C,N,V,S | 2
MUL | Rd,Rr | Multiply Unsigned | R1:R0 = Rd * Rr | Z,C | 2
MULS | Rd,Rr | Multiply Signed | R1:R0 = Rd * Rr | Z,C | 2
MULSU | Rd,Rr | Multiply Signed with Unsigned | R1:R0 = Rd * Rr | Z,C | 2
FMUL | Rd,Rr | Fractional Multiply Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
FMULS | Rd,Rr | Fractional Multiply Signed | R1:R0 = (Rd *Rr) << 1 | Z,C | 2
FMULSU | Rd,Rr | Fractional Multiply Signed with Unsigned | R1:R0 = (Rd * Rr) << 1 | Z,C | 2
DES (*) | K | Data Encryption Standard | Encrypt/Decrypt round (R0-R7, R15-R8, K) | None | 1(2)

(*) DES instruction is only supported on devices with hardware DES crypto engine. Consult the device data sheet for more information.

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
EIJMP | None | Extended Indirect Jump (Z) | PC(15:0) = Z, PC(21:16) = EIND | None | 2
JMP | k | Jump | PC = k | None | 3
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
EICALL | None | Extended Indirect Call (Z) | STACK = PC+1, PC(15:0) = Z, PC(21:16) = EIND | None | 4
CALL | k | Call Subroutine | STACK = PC+2, PC = k | None | 4/5*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
MOVW | Rd,Rr | Copy register pair | Rd+1:Rd = Rr+1:Rr, r,d even | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct | Rd = (k) | None | 2*
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LDD | Rd,Y+q | Load Indirect with displacement | Rd = (Y+q) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
LDD | Rd,Z+q | Load Indirect with displacement | Rd = (Z+q) | None | 2*
STS | k,Rr | Store Direct | (k) = Rr | None | 2*
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Y+q,Rr | Store Indirect with displacement | (Y+q) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
ST | Z+q,Rr | Store Indirect with displacement | (Z+q) = Rr | None | 2
LPM | None | Load Program Memory | R0 = (Z) | None | 3
LPM | Rd,Z | Load Program Memory | Rd = (Z) | None | 3
LPM | Rd,Z+ | Load Program Memory and Post-Increment | Rd = (Z), Z=Z+1 | None | 3
ELPM | None | Extended Load Program Memory | R0 = (RAMPZ:Z) | None | 3
ELPM | Rd,Z | Extended Load Program Memory | Rd = (RAMPZ:Z) | None | 3
ELPM | Rd,Z+ | Extended Load Program Memory and Post-Increment | Rd = (RAMPZ:Z), Z = Z+1 | None | 3
SPM | None | Store Program Memory | (RAMPZ:Z) = R1:R0 [, Z = Z + 2] | None | -
IN | Rd,P | In Port | Rd = P | None | 1
OUT | P,Rr | Out Port | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1

MCU Control Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK | None | Execution Break | See instruction manual | None | 1

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
Rdl: R24, R26, R28, R30. For ADIW and SBIW instructions
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


ATtiny10 Instruction Set

AVR8L Instruction Set

Devices using the AVR8L CPU: ATtiny10, ATtiny20, ATtiny40.

The AVR8L CPU core is a low-cost version of the AVR, and lacks certain features found in regular AVR, most notably:

  • Register file is 16 registers instead of 32 (R16-R31). The assembler will produce an error message if registers R0-R15 are used.

  • Instruction set is reduced, see table below. Notice that the LDS/STS instructions are different from regular AVRs, it is a 1-word instruction with an addressing range of 128 bytes. Also notice that the LPM instruction is eliminated; the Flash memory is mapped into data memory and can be read by means of using the LD instruction.

Arithmetic and Logic Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
ADD | Rd,Rr | Add without Carry | Rd = Rd + Rr | Z,C,N,V,H,S | 1
ADC | Rd,Rr | Add with Carry | Rd = Rd + Rr + C | Z,C,N,V,H,S | 1
SUB | Rd,Rr | Subtract without Carry | Rd = Rd - Rr | Z,C,N,V,H,S | 1
SUBI | Rd,K8 | Subtract Immediate | Rd = Rd - K8 | Z,C,N,V,H,S | 1
SBC | Rd,Rr | Subtract with Carry | Rd = Rd - Rr - C | Z,C,N,V,H,S | 1
SBCI | Rd,K8 | Subtract with Carry Immedtiate | Rd = Rd - K8 - C | Z,C,N,V,H,S | 1
AND | Rd,Rr | Logical AND | Rd = Rd · Rr | Z,N,V,S | 1
ANDI | Rd,K8 | Logical AND with Immediate | Rd = Rd · K8 | Z,N,V,S | 1
OR | Rd,Rr | Logical OR | Rd = Rd V Rr | Z,N,V,S | 1
ORI | Rd,K8 | Logical OR with Immediate | Rd = Rd V K8 | Z,N,V,S | 1
EOR | Rd,Rr | Logical Exclusive OR | Rd = Rd EOR Rr | Z,N,V,S | 1
COM | Rd | One's Complement | Rd = $FF - Rd | Z,C,N,V,S | 1
NEG | Rd | Two's Complement | Rd = $00 - Rd | Z,C,N,V,H,S | 1
SBR | Rd,K8 | Set Bit(s) in Register | Rd = Rd V K8 | Z,C,N,V,S | 1
CBR | Rd,K8 | Clear Bit(s) in Register | Rd = Rd · ($FF - K8) | Z,C,N,V,S | 1
INC | Rd | Increment Register | Rd = Rd + 1 | Z,N,V,S | 1
DEC | Rd | Decrement Register | Rd = Rd -1 | Z,N,V,S | 1
TST | Rd | Test for Zero or Negative | Rd = Rd · Rd | Z,C,N,V,S | 1
CLR | Rd | Clear Register | Rd = 0 | Z,C,N,V,S | 1
SER | Rd | Set Register | Rd = $FF | None | 1

Branch Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
RJMP | k | Relative Jump | PC = PC + k +1 | None | 2
IJMP | None | Indirect Jump to (Z) | PC = Z | None | 2
RCALL | k | Relative Call Subroutine | STACK = PC+1, PC = PC + k + 1 | None | 3/4*
ICALL | None | Indirect Call to (Z) | STACK = PC+1, PC = Z | None | 3/4*
RET | None | Subroutine Return | PC = STACK | None | 4/5*
RETI | None | Interrupt Return | PC = STACK | I | 4/5*
CPSE | Rd,Rr | Compare, Skip if equal | if (Rd ==Rr) PC = PC 2 or 3 | None | 1/2/3
CP | Rd,Rr | Compare | Rd -Rr | Z,C,N,V,H,S | 1
CPC | Rd,Rr | Compare with Carry | Rd - Rr - C | Z,C,N,V,H,S | 1
CPI | Rd,K8 | Compare with Immediate | Rd - K | Z,C,N,V,H,S | 1
SBRC | Rr,b | Skip if bit in register cleared | if(Rr(b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBRS | Rr,b | Skip if bit in register set | if(Rr(b)==1) PC = PC + 2 or 3 | None | 1/2/3
SBIC | P,b | Skip if bit in I/O register cleared | if(I/O(P,b)==0) PC = PC + 2 or 3 | None | 1/2/3
SBIS | P,b | Skip if bit in I/O register set | if(I/O(P,b)==1) PC = PC + 2 or 3 | None | 1/2/3
BRBC | s,k | Branch if Status flag cleared | if(SREG(s)==0) PC = PC + k + 1 | None | 1/2
BRBS | s,k | Branch if Status flag set | if(SREG(s)==1) PC = PC + k + 1 | None | 1/2
BREQ | k | Branch if equal | if(Z==1) PC = PC + k + 1 | None | 1/2
BRNE | k | Branch if not equal | if(Z==0) PC = PC + k + 1 | None | 1/2
BRCS | k | Branch if carry set | if(C==1) PC = PC + k + 1 | None | 1/2
BRCC | k | Branch if carry cleared | if(C==0) PC = PC + k + 1 | None | 1/2
BRSH | k | Branch if same or higher | if(C==0) PC = PC + k + 1 | None | 1/2
BRLO | k | Branch if lower | if(C==1) PC = PC + k + 1 | None | 1/2
BRMI | k | Branch if minus | if(N==1) PC = PC + k + 1 | None | 1/2
BRPL | k | Branch if plus | if(N==0) PC = PC + k + 1 | None | 1/2
BRGE | k | Branch if greater than or equal (signed) | if(S==0) PC = PC + k + 1 | None | 1/2
BRLT | k | Branch if less than (signed) | if(S==1) PC = PC + k + 1 | None | 1/2
BRHS | k | Branch if half carry flag set | if(H==1) PC = PC + k + 1 | None | 1/2
BRHC | k | Branch if half carry flag cleared | if(H==0) PC = PC + k + 1 | None | 1/2
BRTS | k | Branch if T flag set | if(T==1) PC = PC + k + 1 | None | 1/2
BRTC | k | Branch if T flag cleared | if(T==0) PC = PC + k + 1 | None | 1/2
BRVS | k | Branch if overflow flag set | if(V==1) PC = PC + k + 1 | None | 1/2
BRVC | k | Branch if overflow flag cleared | if(V==0) PC = PC + k + 1 | None | 1/2
BRIE | k | Branch if interrupt enabled | if(I==1) PC = PC + k + 1 | None | 1/2
BRID | k | Branch if interrupt disabled | if(I==0) PC = PC + k + 1 | None | 1/2

Data Transfer Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
MOV | Rd,Rr | Copy register | Rd = Rr | None | 1
LDI | Rd,K8 | Load Immediate | Rd = K | None | 1
LDS | Rd,k | Load Direct from SRAM | Rd = (k) | None | 1
LD | Rd,X | Load Indirect | Rd = (X) | None | 2*
LD | Rd,X+ | Load Indirect and Post-Increment | Rd = (X), X=X+1 | None | 2*
LD | Rd,-X | Load Indirect and Pre-Decrement | X=X-1, Rd = (X) | None | 2*
LD | Rd,Y | Load Indirect | Rd = (Y) | None | 2*
LD | Rd,Y+ | Load Indirect and Post-Increment | Rd = (Y), Y=Y+1 | None | 2*
LD | Rd,-Y | Load Indirect and Pre-Decrement | Y=Y-1, Rd = (Y) | None | 2*
LD | Rd,Z | Load Indirect | Rd = (Z) | None | 2*
LD | Rd,Z+ | Load Indirect and Post-Increment | Rd = (Z), Z=Z+1 | None | 2*
LD | Rd,-Z | Load Indirect and Pre-Decrement | Z=Z-1, Rd = (Z) | None | 2*
STS | k,Rr | Store Direct to SRAM | (k) = Rr | None | 1
ST | X,Rr | Store Indirect | (X) = Rr | None | 2*
ST | X+,Rr | Store Indirect and Post-Increment | (X) = Rr, X=X+1 | None | 2*
ST | -X,Rr | Store Indirect and Pre-Decrement | X=X-1, (X)=Rr | None | 2*
ST | Y,Rr | Store Indirect | (Y) = Rr | None | 2*
ST | Y+,Rr | Store Indirect and Post-Increment | (Y) = Rr, Y=Y+1 | None | 2
ST | -Y,Rr | Store Indirect and Pre-Decrement | Y=Y-1, (Y) = Rr | None | 2
ST | Z,Rr | Store Indirect | (Z) = Rr | None | 2
ST | Z+,Rr | Store Indirect and Post-Increment | (Z) = Rr, Z=Z+1 | None | 2
ST | -Z,Rr | Store Indirect and Pre-Decrement | Z=Z-1, (Z) = Rr | None | 2
IN | Rd,P | In from I/O location | Rd = P | None | 1
OUT | P,Rr | Out to I/O location | P = Rr | None | 1
PUSH | Rr | Push register on Stack | STACK = Rr | None | 2
POP | Rd | Pop register from Stack | Rd = STACK | None | 2

Bit and Bit-test Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
LSL | Rd | Logical shift left | Rd(n+1)=Rd(n), Rd(0)=0, C=Rd(7) | Z,C,N,V,H,S | 1
LSR | Rd | Logical shift right | Rd(n)=Rd(n+1), Rd(7)=0, C=Rd(0) | Z,C,N,V,S | 1
ROL | Rd | Rotate left through carry | Rd(0)=C, Rd(n+1)=Rd(n), C=Rd(7) | Z,C,N,V,H,S | 1
ROR | Rd | Rotate right through carry | Rd(7)=C, Rd(n)=Rd(n+1), C=Rd(0) | Z,C,N,V,S | 1
ASR | Rd | Arithmetic shift right | Rd(n)=Rd(n+1), n=0,...,6 | Z,C,N,V,S | 1
SWAP | Rd | Swap nibbles | Rd(3..0) = Rd(7..4), Rd(7..4) = Rd(3..0) | None | 1
BSET | s | Set flag | SREG(s) = 1 | SREG(s) | 1
BCLR | s | Clear flag | SREG(s) = 0 | SREG(s) | 1
SBI | P,b | Set bit in I/O register | I/O(P,b) = 1 | None | 2
CBI | P,b | Clear bit in I/O register | I/O(P,b) = 0 | None | 2
BST | Rr,b | Bit store from register to T | T = Rr(b) | T | 1
BLD | Rd,b | Bit load from register to T | Rd(b) = T | None | 1
S EC | None | Set carry flag | C =1 | C | 1
CLC | None | Clear carry flag | C = 0 | C | 1
SEN | None | Set negative flag | N = 1 | N | 1
CLN | None | Clear negative flag | N = 0 | N | 1
SEZ | None | Set zero flag | Z = 1 | Z | 1
CLZ | None | Clear zero flag | Z = 0 | Z | 1
SEI | None | Set interrupt flag | I = 1 | I | 1
CLI | None | Clear interrupt flag | I = 0 | I | 1
SES | None | Set signed flag | S = 1 | S | 1
CLN | None | Clear signed flag | S = 0 | S | 1
SEV | None | Set overflow flag | V = 1 | V | 1
CLV | None | Clear overflow flag | V = 0 | V | 1
SET | None | Set T-flag | T = 1 | T | 1
CLT | None | Clear T-flag | T = 0 | T | 1
SEH | None | Set half carry flag | H = 1 | H | 1
CLH | None | Clear half carry flag | H = 0 | H | 1

MCU Control Instructions

Mnemonic | Operands | Description | Operation | Flags | Cycles
NOP | None | No operation | None | None | 1
SLEEP | None | Sleep | See instruction manual | None | 1
WDR | None | Watchdog Reset | See instruction manual | None | 1
BREAK (*) | None | Execution Break | See instruction manual | None | 1

(*) BREAK only supported on devices with On-Chip Debug feature.

The Assembler is not case sensitive.

The operands have the following forms:

Rd: Destination (and source) register in the register file
Rr: Source register in the register file
b: Constant (0-7), can be a constant expression
s: Constant (0-7), can be a constant expression
P: Constant (0-31/63), can be a constant expression
K6; Constant (0-63), can be a constant expression
K8: Constant (0-255), can be a constant expression
k: Constant, value range depending on instruction. Can be a constant expression
q: Constant (0-63), can be a constant expression
X,Y,Z: Indirect address registers (X=R27:R26, Y=R29:R28, Z=R31:R30)


Instruction Set Nomenclature:

Status Register (SREG)

SREG : Status register

C : Carry flag in status register

Z : Zero flag in status register

N : Negative flag in status register

V : Two's complement overflow indicator

S : N [+] V, For signed tests

H : Half Carry flag in the status register

T : Transfer bit used by BLD and BST instructions

I : Global interrupt enable/disable flag

Registers and Operands

Rd : Destination (and source) register in the register file

Rr : Source register in the register file

R : Result after instruction is executed

K : Constant data

k : Constant address

b : Bit in the register file or I/O register (3 bit)

s: Bit in the status register (3 bit)

X,Y,Z : Indirect address register (X=R27:R26, Y=R29:R28 and Z=R31:R30)

A : I/O location address

q : Displacement for direct addressing (6 bit)


I/O Registers

RAMPX, RAMPY, RAMPZ

Registers concatenated with the X, Y and Z registers enabling indirect addressing of the whole data space on MCUs with more than 64K bytes data space, and constant data fetch on MCUs with more than 64K bytes program space.

RAMPD

Register concatenated with the Z register enabling direct addressing of the whole data space on MCUs with more than 64K bytes data space.

EIND

Register concatenated with the instruction word enabling indirect jump and call to the whole program space on MCUs with more than 128K bytes program space.

Stack

STACK:Stack for return address and pushed registers

SP:Stack Pointer to STACK

Flags

<>  :Flag affected by instruction

0   :Flag cleared by instruction

1   :Flag set by instruction

-   :Flag not affected by instruction


ADC - Add with Carry

Description:
Adds two registers and the contents of the C flag and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd + Rr + C

Syntax:                     Operands:                           Program Counter:

(i)ADC Rd,                  Rr0 ≤ d ≤ 31, 0 ≤ r ≤ 31            PC <-  PC + 1

16-bit Opcode:

0001

11rd

dddd

rrrr

Status Register (SREG) Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H:Rd3 • Rr3+Rr3 • R3 + R3 • Rd3 Set if there was a carry from bit 3; cleared otherwise

S: N [+] V For signed tests.

V:Rd7 • Rr7 • R7 + Rd7 • Rr7 • R7 Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; cleared otherwise.

C:Rd7 • Rr7 + Rr7 • R7 + R7 • Rd7 Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

             ; Add R1:R0 to R3:R2

add r2,r0    ; Add low byte

adc r3,r1    ; Add with carry high byte

Words: 1 (2 bytes)

Cycles: 1


ADD - Add without Carry

Description:

Adds two registers without the C flag and places the result in the destination register Rd.

Operation:

Rd <- Rd + Rr

Syntax:                  Operands:                                   Program Counter:

ADD Rd,Rr                0 ≤ d ≤ 31, 0 ≤ r ≤ 31                      PC <- PC + 1

16-bit Opcode:

0000

11rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H:Rd3 • Rr3+Rr3 • R3 + R3 • Rd3

Set if there was a carry from bit 3; cleared otherwise

S: N [+] V, For signed tests.

V:Rd7 • Rr7 • R7 + Rd7 • Rr7 • R7 Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; cleared otherwise.

C:Rd7 • Rr7 +Rr7 • R7 + R7 • Rd7 Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

add r1,r2               ; Add r2 to r1 (r1=r1+r2)

add r28, r28            ; Add r28 to itself (r28=r28+r28)

Words: 1 (2 bytes)

Cycles: 1


ADIW - Add Immediate to Word

Description:

Adds an immediate value (0-63) to a register pair and places the result in the register pair. This instruction operates on the upper four register pairs, and is well suited for operations on the pointer registers.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i)Rd+1:Rd <- Rd+1:Rd + K

Syntax:                Operands:                                   Program Counter:

(i)ADIW Rd+1:Rd,K      d E {24,26,28,30}, 0 <= K <= 63             PC <- PC + 1

16-bit Opcode:

1001

0110

KKdd

KKKK

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | <> | <> | <> | <> | <>

S: N [+] V, For signed tests.

V:Rdh7 • R15

Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R15

Set if MSB of the result is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

C: R15 • Rdh7

Set if there was carry from the MSB of the result; cleared otherwise.

R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 = R15-R8, Rdl7-Rdl0=R7-R0).

Example:

adiw r25:24,1                             ; Add 1 to r25:r24

adiw ZH:ZL,63                             ; Add 63 to the Z pointer(r31:r30)

Words: 1 (2 bytes)

Cycles: 2


AND - Logical AND

Description:

Performs the logical AND between the contents of register Rd and register Rr and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd • Rr

Syntax:          Operands:                     Program Counter:

(i)AND Rd,Rr     0 ≤ d ≤ 31, 0 ≤ r ≤ 31        PC ← PC + 1

16-bit Opcode:

0010

00rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N [+] V,

For signed tests.

V:0

Cleared

N:

R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

R

(Result) equals Rd after the operation.

Example:

and r2,r3 ; Bitwise and r2 and r3, result in r2

ldi r16,1 ; Set bitmask 0000 0001 in r16

and r2, r16 ; Isolate bit 0 in r2

Words: 1 (2 bytes)

Cycles: 1


ANDI - Logical AND with Immediate

Description:

Performs the logical AND between the contents of register Rd and a constant and places the result in the destination register Rd.

Operation:

 (i)Rd ← Rd • K

Syntax:           Operands:                         Program Counter:

 (i)ANDI Rd,K     16 ≤ d ≤ 31, 0 ≤ K ≤ 255          PC ← PC + 1

16-bit Opcode:

0111

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N [+] V, For signed tests.

V:0 Cleared

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

andi r17,$0F          ; Clear upper nibble of r17

andi r18,$10          ; Isolate bit 4 in r18

andi r19,$AA          ; Clear odd bits of r19

Words: 1 (2 bytes)

Cycles: 1


ASR - Arithmetic Shift Right

Description:

Shifts all bits in Rd one place to the right. Bit 7 is held constant. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides a signed value by two without changing its sign. The carry flag can be used to round the result.

Operation:

(i)

Syntax:                Operands:                    Program Counter:

(i)ASR R               d0 ≤ d ≤ 31                  PC ← PC + 1

16-bit Opcode:

1001

010d

dddd

0101

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | <> | <> | <> | <> | <>

S: N [+] V,

For signed tests.

V:N [+] C

(For N and C after the shift)

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C:Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

dir 16,$10              ; Load decimal 16 into r16

asr r16                 ; r16=r16 / 2

ldi r17,$FC             ; Load -4 in r17

asr r17                 ; r17=r17/2

Words: 1 (2 bytes)

Cycles: 1


BCLR - Bit Clear in SREG

Description:

Clears a single flag in SREG.

Operation:

(i)SREG(s) ← 0

Syntax:                     Operands:                      Program Counter:

(i)BCLR s                   0 ≤ s ≤ 7                      PC <- PC + 1

16-bit Opcode:

1001

0100

1sss

1000

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
<> | <> | <> | <> | <> | <> | <> | <>

I:0 if s = 7; Unchanged otherwise.

T:0 if s = 6; Unchanged otherwise.

H:0 if s = 5; Unchanged otherwise.

S:0 if s = 4; Unchanged otherwise.

V:0 if s = 3; Unchanged otherwise.

N:0 if s = 2; Unchanged otherwise.

Z:0 if s = 1; Unchanged otherwise.

C:0 if s = 0; Unchanged otherwise.

Example:

bclr 0; Clear carry flag

bclr 7; Disable interrupts

Words: 1 (2 bytes)

Cycles: 1


BLD - Bit Load from the T Flag in SREG to a Bit in Register.

Description:

Copies the T flag in the SREG (status register) to bit b in register Rd.

Operation:

Rd(b) <- T

Syntax:                          Operands:                      Program Counter:

BLD Rd,b                         0 ≤ d ≤ 31, 0 ≤ b ≤ 7          PC <- PC + 1

16 bit Opcode:

1111

100d

dddd

0bbb

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

; Copy bit

bst r1,2         ; Store bit 2 of r1 in T flag

bld r0, 4        ; Load T flag into bit 4 of r0

Words: 1 (2 bytes)

Cycles: 1


BRBC - Branch if Bit in SREG is Cleared

Description:

Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is
represented in two's complement form.

Operation:

If SREG(s) = 0 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:                 Operands:                     Program Counter:

BRBC s, k               0 ≤ s ≤ 7, -64 ≤ k ≤ +63      PC <- PC + k + 1

PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

ksss

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cpi r20,5        ; Compare r20 to the value 5

brbc 1,noteq     ; Branch if zero flag cleared

...

noteq:nop        ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRBS - Branch if Bit in SREG is Set

Description:

Conditional relative branch. Tests a single bit in SREG and branches relatively to PC if the bit is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form.

Operation:

If SREG(s) = 1 then PC ← PC + k + 1, else PC ← PC + 1

Syntax:                  Operands:                          Program Counter:

BRBS s,k                 0 ≤ s ≤ 7, -64 ≤ k ≤ +63           PC <- PC + k + 1

                                                            PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

ksss

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

bstr 0,3             ; Load T bit with bit 3 of r0

brbs 6, bitset       ; Branch T bit was set

...

bitset:    nop                  ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRCC - Branch if Carry Cleared

Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 0,k).

Operation:

If C = 0 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:               Operands:                     Program Counter:

BRCC k                -64 ≤ k ≤ +63                 PC <- PC + k + 1

                                                    PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k000

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

add  r22,r23               ; Add r23 to r22

brcc nocarry               ; Branch if carry cleared

...

nocarry:   nop                        ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRCS - Branch if Carry Set

Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 0,k).

Operation:

If C = 1 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:             Operands:                        Program Counter:

BRCS k              -64 ≤ k ≤ +63                    PC <- PC + k + 1

                                                     PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k000

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cpi r26, $56                ; Compare r26 with $56

brcs carry                  ; Branch if carry set

...

carry:      nop                        ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BREAK - Break

Description:

The BREAK instruction is used by the On-Chip Debug system, and is normally not used in the application software. When the BREAK instruction is executed, the AVR CPU is set in the Stopped Mode. This gives the On-Chip Debugger access to internal resources.

If any lock bits are set, or either the JTAGEN or OCDEN fuses are unprogrammed, the CPU will treat the BREAK instruction as a NOP and will not enter the Stopped Mode.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

On-Chip Debug system break.

Syntax:               Operands:                Program Counter:

BREAK                 None                     PC <- PC + 1

16-bit Opcode:

1001

0101

1001

1000

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Words: 1 (2 bytes)

Cycles: 1


BREQ - Branch if Equal

Description:

Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned or signed binary number represented in Rd was equal to the unsigned or signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 1,k).

Operation:

If Rd = Rr (Z = 1) then PC <- PC + k + 1, else PC <- PC + 1

Syntax:                Operands:                    Program Counter:

BREQ k                 -64 ≤ k ≤ +63                PC <- PC + k + 1

                                                    PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k001

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cp        r1, r0           ; Compare registers r1 and r0

breq     equal             ; Branch if registers equal

...

equal:     nop                        ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRGE - Branch if Greater or Equal (Signed)

Description:

Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signed binary number represented in Rd was greater than or equal to the signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 4,k).

Operation:

If Rd ≥ Rr (N ⊕ V = 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax:              Operands:                       Program Counter:

BRGE k               k-64 ≤ k ≤ +63                  PC <- PC + k + 1

                                                     PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k100

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cp     r11,r12             ; Compare registers r11 and r12

brge   greateq             ; Branch if r11 ≥ r12 (signed)

...

greateq:   nop                        ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRHC - Branch if Half Carry Flag is Cleared

Description:

Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 5,k).

Operation:

If H = 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax:              Operands:                       Program Counter:

BRHC k               -64 ≤ k ≤ +63                   PC <- PC + k + 1

PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k101

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

brhc hclear            ; Branch if half carry flag cleared

...

hclear:    nop                    ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRHS - Branch if Half Carry Flag is Set

Description:

Conditional relative branch. Tests the Half Carry flag (H) and branches relatively to PC if H is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 5,k).

Operation:

If H = 1 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:            Operands:                      Program Counter:

BRHS k             -64 ≤ k ≤ +63                  PC <- PC + k + 1

                                                  PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k101

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

brhs hset        ; Branch if half carry flag set

...

hset:      nop               ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRID - Branch if Global Interrupt is Disabled

Description:

Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 7,k).

Operation:

If I = 0 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:         Operands:                    Program Counter:

BRID k          -64 ≤ k ≤ +63                PC <- PC + k + 1

                                             PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

brid intdis ; Branch if interrupt disabled

...

intdis:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRIE - Branch if Global Interrupt is Enabled

Description:

Conditional relative branch. Tests the Global Interrupt flag (I) and branches relatively to PC if I is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 7,k).

Operation:

If I = 1 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:          Operands:                Program Counter:

BRIE k           -64 ≤ k ≤ +63            PC ← PC + k + 1

                                          PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

brie inten ; Branch if interrupt enabled

...

inten:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRLO - Branch if Lower (Unsigned)

Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned binary number represented in Rd was smaller than the unsigned binary number represented in Rr. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 0,k).

Operation:

If Rd < Rr (C = 1) then PC <- PC + k + 1, else PC <- PC + 1

Syntax:           Operands:                    Program Counter:

BRLO k            -64 ≤ k ≤ +63                PC <- PC + k + 1

                                               PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k000

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

eor r19,r19 ; Clear r19

loop:incr19 ; Increase r19

...

cpi r19,$10 ; Compare r19 with $10

brlo loop ; Branch if r19 < $10 (unsigned)

nop ; Exit from loop (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRLT - Branch if Less Than (Signed)

Description:

Conditional relative branch. Tests the Signed flag (S) and branches relatively to PC if S is set. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the signed binary number represented in Rd was less than the signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 4,k).

Operation:

If Rd < Rr (N [+] V = 1) then PC <- PC + k + 1, else PC <- PC + 1

Syntax:           Operands:                      Program Counter:

BRLT k            -64 ≤ k ≤ +63                  PC <- PC + k + 1

                                                 PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k100

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cp r16,r1 ; Compare r16 to r1

brlt less ; Branch if r16 < r1 (signed)

...

less:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRMI - Branch if Minus

Description:

Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 2,k).

Operation:

If N = 1 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:              Operands:                       Program Counter:

BRMI k               -64 ≤ k ≤ +63                   PC <- PC + k + 1

                                                     PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k010

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

subi r18,4           ; Subtract 4 from r18

brmi negative        ; Branch if result negative

...

negative:  nop                  ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRNE - Branch if Not Equal

Description:

Conditional relative branch. Tests the Zero flag (Z) and branches relatively to PC if Z is cleared. If the instruction is executed immediately after any of the instructions CP, CPI, SUB or SUBI, the branch will occur if and only if the unsigned or signed binary number represented in Rd was not equal to the unsigned or signed binary number represented in Rr. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 1,k).

Operation:

If Rd ≠ Rr (Z = 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax:            Operands:                     Program Counter:

BRNE k             -64 ≤ k ≤ +63                 PC <- PC + k + 1

                                                 PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k001

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

eor r27,r27 ; Clear r27

loop:inc r27 ; Increase r27

...

cpir27,5 ; Compare r27 to 5

brneloop ; Branch if r27<>5

nop ; Loop exit (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRPL - Branch if Plus

Description:

Conditional relative branch. Tests the Negative flag (N) and branches relatively to PC if N is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 2,k).

Operation:

If N = 0 then PC ← PC + k + 1, else PC ← PC + 1

Syntax:            Operands:                     Program Counter:

BRPL k             -64 ≤ k ≤ +63                 PC <- PC + k + 1

                                                 PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k010

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

subi r26,$50 ; Subtract $50 from r26

brpl positive ; Branch if r26 positive

...

positive:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRSH - Branch if Same or Higher (Unsigned)

Description:

Conditional relative branch. Tests the Carry flag (C) and branches relatively to PC if C is cleared. If the instruction is executed immediately after execution of any of the instructions CP, CPI, SUB or SUBI the branch will occur if and only if the unsigned binary number represented in Rd was greater than or equal to the unsigned binary number represented in Rr. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 0,k).

Operation:

If Rd ≥Rr (C = 0) then PC ← PC + k + 1, else PC ← PC + 1

Syntax:             Operands:                  Program Counter:

BRSH k              -64 ≤ k ≤ +63              PC <- PC + k + 1

                                               PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

subi r19,4 ; Subtract 4 from r19

brsh highsm ; Branch if r19 >= 4 (unsigned)

...

highsm:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRTC - Branch if the T Flag is Cleared

Description:

Conditional relative branch. Tests the T flag and branches relatively to PC if T is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 6,k).

Operation:

If T = 0 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:            Operands:                      Program Counter:

BRTC k             -64 ≤ k ≤ +63                  PC <- PC + k + 1

                                                  PC <- PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k110

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

bst r3,5 ; Store bit 5 of r3 in T flag

brtc tclear ; Branch if this bit was cleared

...

tclear:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRTS - Branch if the T Flag is Set

Description:

Conditional relative branch. Tests the T flag and branches relatively to PC if T is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 6,k).

Operation:

If T = 1 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:          Operands:                   Program Counter:

BRTS k           -64 ≤ k ≤ +63               PC <- PC + k + 1

PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k110

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

bst r3,5 ; Store bit 5 of r3 in T flag

brts tset ; Branch if this bit was set

...

tset:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRVC - Branch if Overflow Cleared

Description:

Conditional relative branch. Tests the Overflow flag (V) and branches relatively to PC if V is cleared. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBC 3,k).

Operation:

If V = 0 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:       Operands:                  Program Counter:

BRVC k        -64 ≤ k ≤ +63              PC <- PC + k + 1

                                         PC ← PC + 1, if condition is false

16-bit Opcode:

1111

01kk

kkkk

k011

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

add r3,r4 ; Add r4 to r3

brvc noover ; Branch if no overflow

...

noover:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BRVS - Branch if Overflow Set

Description:

Conditional relative branch. Tests the Overflow flag (V) and branches relatively to PC if V is set. This instruction branches relatively to PC in either direction (PC - 63 ≤ destination ≤ PC + 64). The parameter k is the offset from PC and is represented in two's complement form. (Equivalent to instruction BRBS 3,k).

Operation:

If V = 1 then PC <- PC + k + 1, else PC <- PC + 1

Syntax:               Operands:                   Program Counter:

BRVS k                -64 ≤ k ≤ +63               PC <- PC + k + 1

                                                  PC <- PC + 1, if condition is false

16-bit Opcode:

1111

00kk

kkkk

k011

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

add r3,r4 ; Add r4 to r3

brvs overfl ; Branch if overflow

...

overfl:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false

2 if condition is true


BSET - Bit Set in SREG

Description:

Sets a single flag or bit in SREG.

Operation:

SREG(s) ← 1

Syntax:      Operands:              Program Counter:

BSET s       0 ≤ s ≤ 7              PC ← PC + 1

16-bit Opcode:

1001

0100

0sss

1000

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
<> | <> | <> | <> | <> | <> | <> | <>

I: 1 if s = 7; Unchanged otherwise.

T: 1 if s = 6; Unchanged otherwise.

H: 1 if s = 5; Unchanged otherwise.

S: 1 if s = 4; Unchanged otherwise.

V: 1 if s = 3; Unchanged otherwise.

N: 1 if s = 2; Unchanged otherwise.

Z: 1 if s = 1; Unchanged otherwise.

C: 1 if s = 0; Unchanged otherwie.

Example:

bset 6 ; Set T flag

bset 7 ; Enable interrupt

Words: 1 (2 bytes)

Cycles: 1


BST - Bit Store from Bit in Register to T Flag in SREG

Description:

Stores bit b from Rd to the T flag in SREG (status register).

Operation:

T <- Rd(b)

Syntax:          Operands:                          Program Counter:

BST Rd,b         0 ≤ d ≤ 31, 0 ≤ b ≤ 7              PC <- PC + 1

16-bit Opcode:

1111

101d

dddd

0bbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | <> | - | - | - | - | - | -

T:0 if bit b in Rd is cleared. Set to 1 otherwise.

Example:

; Copy bit

bst r1,2 ; Store bit 2 of r1 in T flag

bld r0,4 ; Load T into bit 4 of r0

Words: 1 (2 bytes)

Cycles: 1


CALL - Long Call to a Subroutine

Description:

Calls to a subroutine within the entire program memory. The return address (to the instruction after the CALL) will be stored onto the stack. (See also RCALL). The stack pointer uses a post-decrement scheme during CALL.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

PC <- kDevices with 16 bits PC, 128K bytes program memory maximum.

PC <- kDevices with 22 bits PC, 8M bytes program memory maximum.

Syntax:         Operands:              Program Counter          Stack:

CALL k          0 ≤ k < 64K            PC <- k                  STACK <- PC+2

                                                                SP <- SP-2, (2 bytes, 16 bits)

CALL k          0 ≤ k < 4M             PC <- k                  STACK <- PC+2

                                                                SP <- SP-3 (3 bytes, 22 bits)

32-bit Opcode:

1001 | 010k | kkkk | 111k
kkkk | kkkk | kkkk | kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

mov r16,r0 ; Copy r0 to r16

call check ; Call subroutine

nop ; Continue (do nothing)

...

check: cpi r16, $42 ; Check if r16 has a special value

breq error ; Branch if equal

ret ; Return from subroutine

...

error: rjmp error ; Infinite loop

Words: 2 (4 bytes)

Cycles:

 | Cycles | Cycles xmega
Devices with 16-bit PC | 4 | 3
Devices with 22-bit PC | 5 | 4


CBI - Clear Bit in I/O Register

Description:

Clears a specified bit in an I/O register. This instruction operates on the lower 32 I/O registers - addresses 0-31.

Operation:

I/O(A,b) <- 0

Syntax:            Operands:                         Program Counter:

CBI A, b           0 ≤ A ≤ 31, 0 ≤ b ≤ 7             PC ← PC + 1

16-bit Opcode:

1001

1000

AAAA

Abbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cbi $12, 7 ; Clear bit 7 in Port D

Words: 1 (2 bytes)

Cycles: 2
Cycles xmega/AVR8L: 1


CBR - Clear Bits in Register

Description:

Clears the specified bits in register Rd. Performs the logical AND between the contents of register Rd and the complement of the constant mask K. The result will be placed in register Rd.

Operation:

Rd <- Rd • ($FF - K)

Syntax:         Operands:                           Program Counter:

CBR Rd,K        16 ≤ d ≤ 31, 0 ≤ K ≤ 255            PC <- PC + 1

16-bit Opcode: (see ANDI with K complemented)

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N ⊕ V, For signed tests.

V:0 Cleared

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

cbr r16, $F0 ; Clear upper nibble of r16

cbr r18, 1 ; Clear bit 0 in r18

Words: 1 (2 bytes)

Cycles: 1


CLC - Clear Carry Flag

Description:

Clears the Carry flag (C) in SREG (status register).

Operation:

C <- 0

Syntax:       Operands:         Program Counter:

CLC           None              PC <- PC + 1

16-bit Opcode:

1001

0100

1000

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | 0

C: 0 Carry flag cleared

Example:

add r0, r0 ; Add r0 to itself

clc ; Clear carry flag

Words: 1 (2 bytes)

Cycles: 1


CLH - Clear Half Carry Flag

Description:

Clears the Half Carry flag (H) in SREG (status register).

Operation:

(i) H ← 0

Syntax:         Operands:               Program Counter:

(i) CLH         None                    PC ← PC + 1

16-bit Opcode:

1001

0100

1101

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | 0 | - | - | - | - | -

H: 0

Half Carry flag cleared

Example:

clh; Clear the Half Carry flag

Words: 1 (2 bytes)

Cycles: 1


CLI - Clear Global Interrupt Flag

Description:

Clears the Global Interrupt flag (I) in SREG (status register). The interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction.

Operation:

I <- 0

Syntax:        Operands:            Program Counter:

CLI            None                 PC <- PC + 1

16-bit Opcode:

1001

0100

1111

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
0 | - | - | - | - | - | - | -

I: 0

Global Interrupt flag cleared

Example:

in temp, SREG ; Store SREG value (temp must be defined by user)

cli ; Disable interrupts during timed sequence

sbi EECR, EEMWE ; Start EEPROM write

sbi EECR, EEWE

out SREG, temp ; Restore SREG value (I-flag)

Words: 1 (2 bytes)

Cycles: 1


CLN - Clear Negative Flag

Description:

Clears the Negative flag (N) in SREG (status register).

Operation:

N <- 0

Syntax:      Operands:          Program Counter:

CLN          None               PC <- PC + 1

16-bit Opcode:

1001

0100

1010

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | 0 | - | -

N: 0 Negative flag cleared

Example:

add r2,r3 ; Add r3 to r2

cln ; Clear negative flag

Words: 1 (2 bytes)

Cycles: 1


CLR - Clear Register

Description:

Clears a register. This instruction performs an Exclusive OR between a register and itself. This will clear all bits in the register.

Operation:

Rd <- Rd [+] Rd

Syntax:      Operands:           Program Counter:

CLR Rd       0 ≤ d ≤ 31          PC <- PC + 1

16-bit Opcode: (see EOR Rd,Rd)

0010

01dd

dddd

dddd

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | 0 | 0 | 0 | 1 | -

S: 0 Cleared

V:0 Cleared

N:0 Cleared

Z:1 Set

R (Result) equals Rd after the operation.

Example:

clr r18 ; clear r18

loop: inc r18 ; increase r18

...

cpi r18, $50 ; Compare r18 to $50

brne loop

Words: 1 (2 bytes)

Cycles: 1


CLS - Clear Signed Flag

Description:

Clears the Signed flag (S) in SREG (status register).

Operation:

S <- 0

Syntax:      Operands:          Program Counter:

CLS          None               PC <- PC + 1

16-bit Opcode:

1001

0100

1100

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | 0 | - | - | - | -

S: 0 Signed flag cleared

Example:

add r2,r3 ; Add r3 to r2

cls ; Clear signed flag

Words: 1 (2 bytes)

Cycles:


CLT - Clear T Flag

Description:

Clears the T flag in SREG (status register).

Operation:

T <- 0

Syntax:      Operands:          Program Counter:

CLT          None               PC <- PC + 1

16-bit Opcode:

1001

0100

1110

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | 0 | - | - | - | - | - | -

T: 0 T flag cleared

Example:

clt ; Clear T flag

Words: 1 (2 bytes)

Cycles: 1


CLV - Clear Overflow Flag

Description:

Clears the Overflow flag (V) in SREG (status register).

Operation:

V <- 0

Syntax:        Operands:            Program Counter:

CLV            None                 PC <- PC + 1

16-bit Opcode:

1001

0100

1011

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | 0 | - | - | -

V: 0 Overflow flag cleared

Example:

add r2,r3 ; Add r3 to r2

clv ; Clear overflow flag

Words: 1 (2 bytes)

Cycles: 1


CLZ - Clear Zero Flag

Description:

Clears the Zero flag (Z) in SREG (status register).

Operation:

Z <- 0

Syntax:          Operands:          Program Counter:

CLZ              None               PC <- PC + 1

16-bit Opcode:

1001

0100

1001

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | 0 | -

Z: 0 Zero flag cleared

Example:

add r2,r3 ; Add r3 to r2

clz; Clear zero

Words: 1 (2 bytes)

Cycles: 1


COM - One's Complement

Description:

This instruction performs a one's complement of register Rd.

Operation:

Rd <- $FF - Rd

Syntax:         Operands:            Program Counter:

COM Rd          0 ≤ d ≤ 31           PC <- PC + 1

16-bit Opcode:

1001
010d
dddd
0000
Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | 1

S:N [+] V For signed tests.

V:0 Cleared.

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; Cleared otherwise.

C:1 Set.

R (Result) equals Rd after the operation.

Example:

com r4 ; Take one's complement of r4

breq zero ; Branch if zero

...

zero: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


CP - Compare

Description:

This instruction performs a compare between two registers Rd and Rr. None of the registers are changed. All conditional branches can be used after this instruction.

Operation:

Rd - Rr

Syntax:         Operands:                         Program Counter:

CP Rd,Rr        0 ≤ d ≤ 31, 0 ≤ r ≤ 31            PC <- PC + 1

16-bit Opcode:

0001

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • Rr3+ Rr3 • R3 +R3 • Rd3 Set if there was a borrow from bit 3; cleared otherwise

S: N [+] V, For signed tests.

V:Rd7 • Rd7 • R7 + Rd7 • Rr7 • R7 Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; cleared otherwise.

C: Rd7 • Rr7+ Rr7 • R7 +R7 • Rd7 Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.

R (Result) after the operation.

Example:

cp r4,r19 ; Compare r4 with r19

brne noteq ; Branch if r4 <> r19

...

noteq: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


CPC - Compare with Carry

Description:

This instruction performs a compare between two registers Rd and Rr and also takes into account the previous carry. None of the registers are changed. All conditional branches can be used after this instruction.

Operation:

Rd - Rr - C

Syntax:          Operands:                          Program Counter:

CPC Rd,Rr        0 ≤ d ≤ 31, 0 ≤ r ≤ 31             PC <- PC + 1

16-bit Opcode:

0000

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • Rr3+ Rr3 • R3 +R3 • Rd3 Set if there was a borrow from bit 3; cleared otherwise

S: N ⊕ V, For signed tests.

V:Rd7 • Rr7 • R7 + Rd7 • Rr7 • R7 Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 • Z Previous value remains unchanged when the result is zero; cleared otherwise.

C: Rd7 • Rr7+ Rr7 • R7 +R7 • Rd7

Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of Rd; cleared otherwise.

R (Result) after the operation.

Example:

; Compare r3:r2 with r1:r0

cp r2,r0 ; Compare low byte

cpc r3,r1 ; Compare high byte

brne noteq ; Branch if not equal

...

noteq:nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


CPI - Compare with Immediate

Description:

This instruction performs a compare between register Rd and a constant. The register is not changed. All conditional branches can be used after this instruction.

Operation:

Rd - K

Syntax:        Operands:                               Program Counter:

CPI Rd,K       16 ≤ d ≤ 31, 0≤ K ≤ 255                 PC <- PC + 1

16-bit Opcode:

0011

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • K3+ K3 • R3+ R3 • Rd3 Set if there was a borrow from bit 3; cleared otherwise

S: N [+] V, For signed tests.

V:Rd7 • K7 • R7 + Rd7 • K7 • R7 Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7 Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 Set if the result is $00; cleared otherwise.

C: Rd7 • K7 +K7 • R7+ R7 • Rd7 Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

R (Result) after the operation.

Example:

cpi r19,3 ; Compare r19 with 3

brne error ; Branch if r19<>3

...

error: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


CPSE - Compare Skip if Equal

Description:

This instruction performs a compare between two registers Rd and Rr, and skips the next instruction if Rd = Rr.

Operation:

If Rd = Rr then PC <- PC + 2 (or 3) else PC <- PC + 1

Syntax:          Operands:                         Program Counter:

CPSE Rd,Rr       0 ≤ d ≤ 31, 0 ≤ r ≤ 31            PC <- PC + 1, Condition false - no skip

                                                   PC <- PC + 2, Skip a one word instruction

                                                   PC ← PC + 3, Skip a two word instruction

16-bit Opcode:

0001

00rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

inc r4 ; Increase r4

cpse r4,r0 ; Compare r4 to r0

neg r4 ; Only executed if r4<>r0

nop ; Continue (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false (no skip)

2 if condition is true (skip is executed) and the instruction skipped is 1 word

3 if condition is true (skip is executed) and the instruction skipped is 2 words


DEC - Decrement

Description:

Subtracts one -1- from the contents of register Rd and places the result in the destination register Rd.

The C flag in SREG is not affected by the operation, thus allowing the DEC instruction to be used on a loop counter in multiple-precision computations.

When operating on unsigned values, only BREQ and BRNE branches can be expected to perform consistently. When operating on two's complement values, all signed branches are available.

Operation:

Rd <- Rd - 1

Syntax:              Operands:                  Program Counter:

DEC Rd               0 ≤ d ≤ 31                 PC <- PC + 1

16-bit Opcode:

1001

010d

dddd

1010

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | <> | <> | <> | -

S:N [+] V

For signed tests.

V: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if two's complement overflow resulted from the operation; cleared otherwise. Two's complement overflow occurs if and only if Rd was $80 before the operation.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; Cleared otherwise.

R (Result) equals Rd after the operation.

Example:

ldi r17, $10 ; Load constant in r17

loop: add r1, r2 ; Add r2 to r1

dec r17 ; Decrement r17

brne loop ; Branch if r17<>0

nop; Continue (do nothing)

Words: 1 (2 bytes)

Cycles: 1


DES - Data Encryption Standard

DES – Data Encryption Standard

Description:

The module is an instruction set extension to the AVR CPU, performing DES iterations. The 64-bit data block (plaintext or ciphertext) is placed in the CPU register file, registers R0-R7, where LSB of data is placed in LSB of R0 and MSB of data is placed in MSB of R7. The full 64-bit key (including parity bits) is placed in registers R8-R15, organized in the register file with LSB of key in LSB of R8 and MSB of key in MSB of R15. Executing one DES instruction performs one round in the DES algorithm. Sixteen rounds must be executed in increasing order to form the correct DES ciphertext or plaintext. Intermediate results are stored in the register file (R0-R15) after each DES instruction. The instruction's operand (K) determines which round is executed, and the half carry flag (H) determines whether encryption or decryption is performed. The DES algorithm is described in "Specifications for the Data Encryption Standard" (Federal Information Processing Standards Publication 46). Intermediate results in this implementation differ from the standard because the initial permutation and the inverse initial permutation are performed each iteration. This does not affect the result in the final ciphertext or plaintext, but reduces execution time.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:
(i) If H = 0 then Encrypt round (R7-R0, R15-R8, K)
If H = 1 then Decrypt round (R7-R0, R15-R8, K)

Syntax: Operands: Program Counter:
(i) DES K 0x00<=K<=0x0F PC <- PC + 1

16-bit Opcode:
1001 0100 KKKK 1011

Example:

DES 0x00
DES 0x01
...
DES 0x0E
DES 0x0F

Words: 1

Cycles: 1 (2(1))

Note: 1. If the DES instruction is succeeding a non-DES instruction, an extra cycle is inserted.


EICALL - Extended Indirect Call to Subroutine

Description:

Indirect call of a subroutine pointed to by the Z (16 bits) pointer register in the register file and the EIND register in the I/O space. This instruction allows for indirect calls to the entire program memory space. The stack pointer uses a post-decrement scheme during EICALL.

This instruction is not implemented for devices with 2 bytes PC, see ICALL. Refer to the device specific instruction set summary.

Operation:

PC(15:0) <- Z(15:0)

PC(21:16) <- EIND

Syntax:        Operands:             Program Counter:              Stack:

EICALL         None                  See Operation                 STACK <- PC + 1

                                                                   SP -< SP - 3 (3 bytes, 22 bits)

16-bit Opcode:

1001

0101

0001

1001

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

ldi r16,$05 ; Set up EIND and Z pointer

out EIND,r16

ldi 30, $00

ldi r31, $10

eicall ; Call to $051000

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega
Only implemented in devices with 22-bit PC | 4 | 3


EIJMP - Extended Indirect Jump

Description:

Indirect jump to the address pointed to by the Z (16 bits) pointer register in the register file and the EIND register in the I/O space. This instruction allows for indirect jumps to the entire program memory space.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

PC(15:0) <- Z(15:0)

PC(21:16) <- EIND

Syntax:     Operands:          Program Counter:             Stack:

EIJMP       None               See Operation                Not Affected

16-bit Opcode:

1001

0100

0001

1001

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

ldi r16, $05 ; Set up EIND and Z pointer

out EIND, r16

ldi r30, $00

ldi r31, $10

eijmp ; Jump to $051000

Words: 1 (2 bytes)

Cycles: 2


ELPM - Extended Load Program Memory

Description:

Loads one byte pointed to by the Z register and the RAMPZ register in the I/O space, and places this byte in the destination register Rd. This instruction features a 100% space effective constant initialization or constant data fetch. The program memory is organized in 16 bit words while the Z pointer is a byte address. Thus, the least significant bit of the Z pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This instruction can address the entire program memory space. The Z pointer register can either be left unchanged by the operation, or it can be incremented. The incrementation applies to the entire 24-bit concatenation of the RAMPZ and Z pointer registers.

Devices with Self-Programming capability can use the ELPM instruction to read the fuse and lock bit value. Refer to the device documentation for a detailed description.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

The result of these combinations is undefined:

ELPM r30, Z+

ELPM r31, Z+

Operation:                                                 Comment:

(1)R0 <- (RAMPZ:Z)                                         RAMPZ:Z: Unchanged, R0 implied destination register

(2)Rd <- (RAMPZ:Z)                                         RAMPZ:Z: Unchanged

(3)Rd <- (RAMPZ:Z) (RAMPZ:Z) <- (RAMPZ:Z) + 1              RAMPZ:Z: Post incremented

Syntax:            Operands:                               Program Counter:

(1) ELPM           None, R0 implied                        PC <- PC + 1

(2) ELPM Rd, Z     0 ≤ d ≤ 31                              PC <- PC + 1

(3) ELPM Rd, Z+    0 ≤ d ≤ 31                              PC <- PC + 1

16 bit Opcode:

(1) | 1001 | 0101 | 1101 | 1000
(2) | 1001 | 000d | dddd | 0110
(3) | 1001 | 000d | dddd | 0111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

ldi ZL, byte3(Table_1<<1) ; Initialize Z pointer

out RAMP Z, ZL

ldi ZH, byte2(Table_1<<1)

ldiZL, byte1(Table_1<<1)

elpm r16, Z+ ; Load constant from program

; memory pointed to by RAMPZ:Z (Z is r31:r30)

...

Table_1:

.dw 0x3738; 0x38 is addressed when ZLSB = 0

; 0x37 is addressed when ZLSB = 1

...

Words: 1 (2 bytes)

Cycles: 3


EOR - Exclusive OR

Description:

Performs the logical EOR between the contents of register Rd and register Rr and places the result in the destination register Rd.

Operation:

Rd <- Rd [+] Rr

Syntax:           Operands:                            Program Counter:

EOR Rd,Rr         0 ≤ d ≤ 31, 0 ≤ r ≤ 31               PC <- PC + 1

16-bit Opcode:

0010

01rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N [+] V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

eor r4,r4 ; Clear r4

eor r0,r22 ; Bitwise exclusive or between r0 and r22

Words: 1 (2 bytes)

Cycles: 1


FMUL - Fractional Multiply Unsigned

Description:

This instruction performs 8-bit × 8-bit → 16-bit unsigned multiplication and shifts the result one bit left.

Rd |  | Rr |  | R1 | R0
Multiplicand | × | Multiplier | -> | Product High | Product Low
8 |  | 8 |  | 16

Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMUL instruction incorporates the shift operation in the same number of cycles as MUL.

The (1.7) format is most commonly used with signed numbers, while FMUL performs an unsigned multiplication. This instruction is therefore most useful for calculating one of the partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. Note: the result of the FMUL operation may suffer from a 2's complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account, and is found in the carry bit. See the following example.

The multiplicand Rd and the multiplier Rr are two registers containing unsigned fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit unsigned fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

R1:R0 ← Rd × Rr(unsigned (1.15) ← unsigned (1.7) × unsigned (1.7))

Syntax:         Operands:                    Program Counter:

FMUL Rd,Rr      16 ≤ d ≤ 23, 16≤ r ≤ 23      PC ← PC + 1

16-bit Opcode:

0000

0011

0ddd

1rrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | <> | <>

C: R16

Set if bit 15 of the result before left shift is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************

;* DESCRIPTION

;*Signed fractional multiply of two 16-bit numbers with 32-bit result.

;* USAGE

;*r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1

;******************************************************************************

fmuls16x16_32:

clr r2

fmuls r23, r21 ;((signed)ah * (signed)bh) << 1

movw r19:r18, r1:r0

fmul r22, r20 ;(al * bl) << 1

adc r18, r2

movw r17:r16, r1:r0

fmulsu r23, r20 ;((signed)ah * bl) << 1

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

fmulsu r21, r22 ;((signed)bh * al) << 1

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

Words: 1 (2 bytes)

Cycles: 2


FMULS - Fractional Multiply Signed

Description:

This instruction performs 8-bit × 8-bit → 16-bit signed multiplication and shifts the result one bit left.

Rd |  | Rr |  | R1 | R0
Multiplicand | × | Multiplier | -> | Product High | Product Low
8 |  | 8 |  | 16 |

Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMULS instruction incorporates the shift operation in the same number of cycles as MULS.

The multiplicand Rd and the multiplier Rr are two registers containing signed fractional numbers where the implicit radix point lies between bit 6 and bit 7. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).

Note that when multiplying 0x80 (-1) with 0x80 (-1), the result of the shift operation is 0x8000 (-1). The shift operation thus gives a two's complement overflow. This must be checked and handled by software.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i)R1:R0 ← Rd × Rr(signed (1.15) <- signed (1.7) × signed (1.7))

Syntax:             Operands:                     Program Counter:

FMULS Rd,Rr         16 ≤ d ≤ 23, 16≤ r ≤ 23       PC <- PC + 1

16-bit Opcode:

0000

0011

1ddd

0rrr

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | ⇔ | ⇔

C: R16

Set if bit 15 of the result before left shift is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

fmuls r23,r22 ; Multiply signed r23 and r22 in (1.7) format, result in (1.15) format

movw r23:r22,r1:r0 ; Copy result back in r23:r22

Words: 1 (2 bytes)

Cycles: 2


FMULSU - Fractional Multiply Signed with Unsigned

Description:

This instruction performs 8-bit × 8-bit → 16-bit signed multiplication and shifts the result one bit left.

Rd |  | Rr |  | R1 | R0
Multiplicand | × | Multiplier | -> | Product High | Product Low
8 |  | 8 |  | 16 |

Let (N.Q) denote a fractional number with N binary digits left of the radix point, and Q binary digits right of the radix point. A multiplication between two numbers in the formats (N1.Q1) and (N2.Q2) results in the format ((N1+N2).(Q1+Q2)). For signal processing applications, the format (1.7) is widely used for the inputs, resulting in a (2.14) format for the product. A left shift is required for the high byte of the product to be in the same format as the inputs. The FMULSU instruction incorporates the shift operation in the same number of cycles as MULSU.

The (1.7) format is most commonly used with signed numbers, while FMULSU performs a multiplication with one unsigned and one signed input. This instruction is therefore most useful for calculating two of the partial products when performing a signed multiplication with 16-bit inputs in the (1.15) format, yielding a result in the (1.31) format. Note: the result of the FMULSU operation may suffer from a 2's complement overflow if interpreted as a number in the (1.15) format. The MSB of the multiplication before shifting must be taken into account, and is found in the carry bit. See the following example.

The multiplicand Rd and the multiplier Rr are two registers containing fractional numbers where the implicit radix point lies between bit 6 and bit 7. The multiplicand Rd is a signed fractional number, and the multiplier Rr is an unsigned fractional number. The 16-bit signed fractional product with the implicit radix point between bit 14 and bit 15 is placed in R1 (high byte) and R0 (low byte).

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

R1:R0 <- Rd × Rr(signed (1.15) ← signed (1.7) × unsigned (1.7))

Syntax:               Operands:                           Program Counter:

FMULSU Rd,Rr          16 ≤ d ≤ 23, 16≤ r ≤ 23             PC <- PC + 1

16-bit Opcode:

0000

0011

1ddd

1rrr

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | ⇔ | ⇔

C: R16

Set if bit 15 of the result before left shift is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************

;* DESCRIPTION

;*Signed fractional multiply of two 16-bit numbers with 32-bit result.

;* USAGE

;*r19:r18:r17:r16 = ( r23:r22 * r21:r20 ) << 1

;******************************************************************************

fmuls16x16_32:

clr r2

fmuls r23, r21 ;((signed)ah * (signed)bh) << 1

movw r19:r18, r1:r0

fmul r22, r20 ;(al * bl) << 1

adc r18, r2

movw r17:r16, r1:r0

fmulsu r23, r20 ;((signed)ah * bl) << 1

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

fmulsu r21, r22;((signed)bh * al) << 1

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

Words: 1 (2 bytes)

Cycles: 2


ICALL - Indirect Call to Subroutine

Description:

Indirect call of a subroutine pointed to by the Z (16 bits) pointer register in the register file. The Z pointer register is 16 bits wide and allows call to a subroutine within the lowest 64K words (128K bytes) section in the program memory space. The stack pointer uses a post-decrement scheme during ICALL.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) PC(15:0) <- Z(15:0)Devices with 16 bits PC, 128K bytes program memory maximum.

(ii) PC(15:0) <- Z(15:0)Devices with 22 bits PC, 8M bytes program memory maximum.

PC(21:16) <- 0

Syntax:              Operands:             Program Counter:                 Stack:

(i) ICALL            None                  See Operation                    STACK <- PC + 1

                                                                            SP <- SP - 2 (2 bytes, 16 bits)

(ii)ICALL            None                  See Operation                    STACK <- PC + 1

                                                                            SP <- SP - 3 (3 bytes, 22 bits)

16-bit Opcode:

1001

0101

0000

1001

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

mov r30,r0 ; Set offset to call table

icall ; Call routine pointed to by r31:r30

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega
Devices with 16-bit PC | 3 | 2
Devices with 22-bit PC | 4 | 3


IJMP - Indirect Jump

Description:

Indirect jump to the address pointed to by the Z (16 bits) pointer register in the register file. The Z pointer register is 16 bits wide and allows jump within the lowest 64K words (128K bytes) section of program memory.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) PC <- Z(15:0) Devices with 16 bits PC, 128K bytes program memory maximum.

(ii) PC(15:0) <- Z(15:0)Devices with 22 bits PC, 8M bytes program memory maximum.

PC(21:16) <- 0

Syntax:              Operands:        Program Counter:          Stack:

(i), (ii) IJMP        None            See Operation             Not Affected

16-bit Opcode:

1001

0100

0000

1001

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

mov r30,r0 ; Set offset to jump table

ijmp ; Jump to routine pointed to by r31:r30

Words: 1 (2 bytes)

Cycles: 2


IN - Load an I/O Location to Register

Description:

Loads data from the I/O Space (Ports, Timers, Configuration registers etc.) into register Rd in the register file.

Operation:

(i)Rd <- I/O(A)

Syntax:        Operands:                          Program Counter:

IN Rd,A        0 ≤ d ≤ 31, 0 ≤ A ≤ 63             PC <- PC + 1

16-bit Opcode:

1011

0AAd

dddd

AAAA

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

in r25,$16 ; Read Port B

cpi r25,4 ; Compare read value to constant

breqexit ; Branch if r25=4

...

exit: nop ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


INC - Increment

Description:

Adds one -1- to the contents of register Rd and places the result in the destination register Rd.

The C flag in SREG is not affected by the operation, thus allowing the INC instruction to be used on a loop counter in multiple-precision computations.

When operating on unsigned numbers, only BREQ and BRNE branches can be expected to perform consistently. When operating on two's complement values, all signed branches are available.

Operation:

(i) Rd <- Rd + 1

Syntax:                 Operands:                  Program Counter:

(i) INC Rd              0 ≤ d ≤ 31                 PC <- PC + 1

16-bit Opcode:

1001

010d

dddd

0011

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | <> | <> | <> | -

S:N [+] V

For signed tests.

V:R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if two's complement overflow resulted from the operation; cleared otherwise. Two's complement overflow occurs if and only if Rd was $7F before the operation.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; Cleared otherwise.

R (Result) equals Rd after the operation.

Example:

clr r22 ; clear r22

loop: inc r22 ; increment r22

...

cpi r22,$4F ; Compare r22 to $4f

brne loop ; Branch if not equal

nop ; Continue (do nothing)

Words: 1 (2 bytes)

Cycles: 1


JMP - Jump

Description:

Jump to an address within the entire 4M (words) program memory. See also RJMP.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i)PC <- k

Syntax:          Operands:               Program Counter:         Stack:

(i)JMP k         0 ≤ k < 4M              PC <- k                  Unchanged

32-bit Opcode:

1001 | 010k | kkkk | 110k
kkkk | kkkk | kkkk | kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

mov r1,r0 ; Copy r0 to r1

jmp farplc ; Unconditional jump

...

farplc:nop ; Jump destination (do nothing)

Words: 2 (4 bytes)

Cycles: 3


LD - Load Indirect from data space to Register using Index X

Description:

Loads one byte indirect from the data space to a register. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

The data location is pointed to by the X (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPX in register in the I/O area has to be changed.

The X pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the X pointer register. Note that only the low byte of the X pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPX register in the I/O area is updated in parts with more than 64K bytes data space or more than 64K bytes program memory, and the increment/decrement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

The result of these combinations is undefined:

LD r26, X+

LD r27, X+

LD r26, -X

LD r27, -X

Using the X pointer:

Operation:                                                         Comment:

(i)Rd <- (X)                                                       X: Unchanged

(ii)Rd <- (X)             X <- X + 1                               X: Post incremented

(iii)X <- X - 1           Rd <- (X)                                X: Pre decremented

Syntax:                   Operands:                                Program Counter:

(i) LD Rd, X              0 ≤ d ≤ 31                               PC <- PC + 1

(ii)LD Rd, X+             0 ≤ d ≤ 31                               PC <- PC + 1

(iii)LD Rd, -X            0 ≤ d ≤ 31                               PC <- PC + 1

16-bit Opcode:

(i) | 1001 | 000d | dddd | 1100
(ii) | 1001 | 000d | dddd | 1101
(iii) | 1001 | 000d | dddd | 1110
Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr r27 ; Clear X high byte

ldi r26,$60 ; Set X low byte to $60

ld r0,X+ ; Load r0 with data space loc. $60(X post inc)

ld r1,X ; Load r1 with data space loc. $61

ldi r26,$63 ; Set X low byte to $63

ld r2,X ; Load r2 with data space loc. $63

ld r3,-X ; Load r3 with data space loc. $62(X pre dec)

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
(i) | 2 | 1/2* | 1/2**
(ii) | 2 | 1/2* | 1/2**
(iii) | 2 | 2/3* | 2/3**

(*) When accessing internal SRAM, one extra cycle is required
(**) When accessing FLASH, one extra cycle is required.


LD (LDD) - Load Indirect from data space to Register using Index Y

Description:

Loads one byte indirect with or without displacement from the data space to a register. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

The data location is pointed to by the Y (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPY in register in the I/O area has to be changed.

The Y pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the Y pointer register. Note that only the low byte of the Y pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY register in the I/O area is updated in parts with more than 64K bytes data space or more than 64K bytes program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

The result of these combinations is undefined:

LD r28, Y+

LD r29, Y+

LD r28, -Y

LD r29, -Y

Using the Y pointer:

Operation:                                                  Comment:

(i)     Rd <- (Y)                                            Y: Unchanged

(ii)    Rd <- (Y)             Y <- Y + 1                     Y: Post incremented

(iii)   Y <- Y - 1            Rd <- (Y)                      Y: Pre decremented

(iiii)* Rd <- (Y+q)                                          Y: Unchanged, q: Displacement

Syntax:                      Operands:                       Program Counter:

(i) LD Rd, Y                 0 ≤ d ≤ 31                      PC <- PC + 1

(ii) LD Rd, Y+               0 ≤ d ≤ 31                      PC <- PC + 1

(iii) LD Rd, -Y              0 ≤ d ≤ 31                      PC <- PC + 1

(iiii)* LDD Rd, Y+q          0 ≤ d ≤ 31, 0 ≤ q ≤ 63          PC <- PC + 1

Notes:

*) The displacement form of this instruction (LDD) is not available on AVR8L based devices.

16-bit Opcode:

(i) | 1000 | 000d | dddd | 1000
(ii) | 1001 | 000d | dddd | 1001
(iii) | 1001 | 000d | dddd | 1010
(iiii) | 10q0 | qq0d | dddd | 1qqq

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr r29 ; Clear Y high byte

ldi r28,$60 ; Set Y low byte to $60

ld r0,Y+ ; Load r0 with data space loc. $60(Y post inc)

ld r1,Y ; Load r1 with data space loc. $61

ldi r28,$63 ; Set Y low byte to $63

ld r2,Y ; Load r2 with data space loc. $63

ld r3,-Y ; Load r3 with data space loc. $62(Y pre dec)

ldd r4,Y+2 ; Load r4 with data space loc. $64

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
(i) | 2 | 1/2* | 1/2**
(ii) | 2 | 1/2* | 1/2**
(iii) | 2 | 2/3* | 2/3**
(iiii) | 2 | 2/3* | N/A

(*) When accessing internal SRAM, one extra cycle is required
(**) When accessing FLASH, one extra cycle is required.


LD (LDD) - Load Indirect From data space to Register using Index Z

Description:

Loads one byte indirect with or without displacement from the data space to a register. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

The data location is pointed to by the Z (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPZ in register in the I/O area has to be changed.

The Z pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for stack pointer usage of the Z pointer register, however because the Z pointer register can be used for indirect subroutine calls, indirect jumps and table lookup, it is often more convenient to use the X or Y pointer as a dedicated stack pointer. Note that only the low byte of the Z pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPZ register in the I/O area is updated in parts with more than 64K bytes data space or more than 64K bytes program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

For using the Z pointer for table lookup in program memory see the LPM and ELPM instructions.

The result of these combinations is undefined:

LD r30, Z+

LD r31, Z+

LD r30, -Z

LD r31, -Z

Using the Z pointer:

Operation:                                              Comment:

(i)     Rd <- (Z)                                        Z: Unchanged

(ii)    Rd <- (Z)                                        Z <- Z + 1Z: Post increment

(iii)   Z <- Z -1 Rd <- (Z)                              Z: Pre decrement

(iiii)* Rd <- (Z+q)                                      Z: Unchanged, q: Displacement

Syntax:                     Operands:                   Program Counter:

(i)     LD Rd, Z              0 ≤ d ≤ 31                 PC <- PC + 1

(ii)    LD Rd, Z+             0 ≤ d ≤ 31                 PC <- PC + 1

(iii)   LD Rd, -Z             0 ≤ d ≤ 31                 PC <- PC + 1

(iiii)* LDD Rd, Z+q           0 ≤ d ≤ 31, 0 ≤ q ≤ 63     PC <- PC + 1

Notes:

*) The displacement form of this instruction (LDD) is not available on AVR8L based devices.

16-bit Opcode:

(i) | 1000 | 000d | dddd | 0000
(ii) | 1001 | 000d | dddd | 0001
(iii) | 1001 | 000d | dddd | 0010
(iiii) | 10q0 | qq0d | dddd | 0qqq

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr r31 ; Clear Z high byte

ldi r30,$60 ; Set Z low byte to $60

ld r0,Z+ ; Load r0 with data space loc. $60(Z post inc)

ld r1,Z ; Load r1 with data space loc. $61

ldi r30,$63 ; Set Z low byte to $63

ld r2,Z ; Load r2 with data space loc. $63

ld r3,-Z ; Load r3 with data space loc. $62(Z pre dec)

ldd r4,Z+2 ; Load r4 with data space loc. $64

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
(i) | 2 | 1/2* | 1/2**
(ii) | 2 | 1/2* | 1/2**
(iii) | 2 | 2/3* | 2/3**
(iiii) | 2 | 2/3* | N/A

(*) When accessing internal SRAM, one extra cycle is required
(**) When accessing FLASH, one extra cycle is required.


LDI - Load Immediate

Description:

Loads an 8 bit constant directly to register 16 to 31.

Operation:

(i)Rd <- K

Syntax:            Operands:                            Program Counter:

(i) LDI Rd,K       16 ≤ d ≤ 31, 0 ≤ K ≤ 255             PC <- PC + 1

16-bit Opcode:

1110

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clrr31 ; Clear Z high byte

ldi r30, $F0 ; Set Z low byte to $F0

lpm ; Load constant from program

; memory pointed to by Z

Words: 1 (2 bytes)

Cycles: 1


LDS - Load Direct from data space

Description:

Loads one byte from the data space to a register. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

A 16-bit address must be supplied. Memory access is limited to the current data segment of 64K bytes. The LDS instruction uses the RAMPD register to access memory above 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPD in register in the I/O area has to be changed.

This instruction is not available in all devices. Refer to the device specific instruction set summary. In particular, notice that AVR8L-based devices use the 1-word LDS instruction instead of this instruction.

Operation:

(i)Rd <- (k)

Syntax:               Operands:                            Program Counter:

(i)LDS Rd,k           0 ≤ d ≤ 31, 0 ≤ k ≤ 65535            PC <- PC + 2

32-bit Opcode:

1001 | 000d | dddd | 0000
kkkk | kkkk | kkkk | kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

lds r2,$FF00 ; Load r2 with the contents of data space location $FF00

add r2,r1 ; add r1 to r2

sts $FF00,r2 ; Write back

Words: 2 (4 bytes)

 | Cycles | Cycles xmega
I/O | 2 | 2
Internal SRAM | 2 | 3


LDS - Load Direct from SRAM

This 1-word form of the LDS instruction is only used on AVR8L-based devices. Other AVR devices use the 2-word LDS instruction.

Description:

Loads one byte from the SRAM section of the data space to a register.

An 8-bit address in the range 0x40 <= k <= 0xBF must be supplied. The assembler will calculate an 7-bit offset into the SRAM memory from this address, hence this instruction is capable of addressing up to 128 bytes of SRAM. This instruction cannot be used to load I/O addresses, use the IN instruction for this purpose.

Operation:

(i)Rd <- (k)

Syntax:               Operands:                            Program Counter:

(i)LDS Rd,k           16 ≤ d ≤ 31, 0x40 ≤ k ≤ 0xBF         PC <- PC + 1

16-bit Opcode:

1010

0kkk

dddd

kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

lds r16,$40 ; Load r16 with the contents of data space location $FF00

add r16,r17 ; add r17 to r16

sts $40,r16 ; Write back

Words: 1 (2 bytes)

Cycles: 1


LPM - Load Program Memory

Description:

Loads one byte pointed to by the Z register into the destination register Rd. This instruction features a 100% space effective constant initialization or constant data fetch. The program memory is organized in 16 bit words while the Z pointer is a byte address. Thus, the least significant bit of the Z pointer selects either low byte (ZLSB = 0) or high byte (ZLSB = 1). This instruction can address the first 64K bytes (32K words) of program memory. The Z pointer register can either be left unchanged by the operation, or it can be incremented. The increment does not apply to the RAMPZ register.

Devices with Self-Programming capability can use the LPM instruction to read the fuse and lock bit values. Refer to the device documentation for a detailed description.

Not all variants of the LPM instruction are available in all devices. Refer to the device specific instruction set summary. The LPM instruction is not implemented at all in the AT90S1200 device.

The result of these combinations is undefined:

LPM r30, Z+

LPM r31, Z+

Operation:                                               Comment:

(i) R0 <- (Z)                                            Z: Unchanged, R0 implied destination register

(ii) Rd <- (Z)                                           Z: Unchanged

(iii) Rd <- (Z)                                          Z <- Z + 1Z: Post incremented

Syntax:                     Operands:                    Program Counter:

(i) LPM                     None, R0 implied             PC <- PC + 1

(ii)LPM Rd, Z               0 ≤ d ≤ 31                   PC <- PC + 1

(iii)LPM Rd, Z+             0 ≤ d ≤ 31                   PC <- PC + 1

16-bit Opcode:

(i) | 1001 | 0101 | 1100 | 1000
(ii) | 1001 | 000d | dddd | 0100
(iii) | 1001 | 000d | dddd | 0101

Status Register (SREG) and Boolean Formula:

I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

ldi ZH, high(Table_1<<1) ; Initialize Z pointer

ldi ZL, low(Table_1<<1)

lpm r16, Z ; Load constant from program

; memory pointed to by Z (r31:r30)

...

Table_1:

.dw 0x5876; 0x76 is addresses when ZLSB = 0

; 0x58 is addresses when ZLSB = 1

...

Words: 1 (2 bytes)

Cycles: 3


LSL - Logical Shift Left

Description:

Shifts all bits in Rd one place to the left. Bit 0 is cleared. Bit 7 is loaded into the C flag of the SREG. This operation effectively multiplies signed and unsigned values by two.

Operation:

C

<-

b7 - - - - - - - - - - - - - - - - - - b0

<-

0

Syntax:           Operands:                 Program Counter:

(i) LSL Rd        0 ≤ d ≤ 31                PC <- PC + 1

16-bit Opcode: (see ADD Rd,Rd)

0000

11dd

dddd

dddd

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3

S: N [+] V, For signed tests.

V: N [+] C (For N and C after the shift)

N: R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C: Rd7

Set if, before the shift, the MSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

add r0, r4 ; Add r4 to r0

lsl r0 ; Multiply r0 by 2

Words: 1 (2 bytes)

Cycles: 1


LSR - Logical Shift Right

Description:

Shifts all bits in Rd one place to the right. Bit 7 is cleared. Bit 0 is loaded into the C flag of the SREG. This operation effectively divides an unsigned value by two. The C flag can be used to round the result.

Operation:

0

->

b7 - - - - - - - - - - - - - - - - - - b0

->

C

Syntax:           Operands:            Program Counter:

(i) LSR Rd        0 ≤ d ≤ 31           PC <- PC + 1

16-bit Opcode:

1001

010d

dddd

0110

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | <> | 0 | <> | <>

S: N [+] V, For signed tests.

V: N [+] C (For N and C after the shift)

N: 0

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C: Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

add r0,r4 ; Add r4 to r0

lsr r0 ; Divide r0 by 2

Words: 1 (2 bytes)

Cycles: 1


MOV - Copy Register

Description:

This instruction makes a copy of one register into another. The source register Rr is left unchanged, while the destination register Rd is loaded with a copy of Rr.

Operation:

(i) Rd <- Rr

Syntax: Operands: Program Counter:

(i) MOV Rd,Rr          0 ≤ d ≤ 31, 0 ≤ r ≤ 31             PC <- PC + 1

16-bit Opcode:

0010

11rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

mov r16,r0 ; Copy r0 to r16

call check ; Call subroutine

...

check: cpi r16,$11 ; Compare r16 to $11

...

ret ; Return from subroutine

Words: 1 (2 bytes)

Cycles: 1

"


MOVW - Copy Register Word

Description:

This instruction makes a copy of one register pair into another register pair. The source register pair Rr+1:Rr is left unchanged, while the destination register pair Rd+1:Rd is loaded with a copy of Rr + 1:Rr.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) Rd+1:Rd <- Rr+1:Rr

Syntax:                        Operands:                                  Program Counter:

(i) MOVW Rd+1:Rd,Rr+1Rr        d E {0,2,...,30}, r E {0,2,...,30}         PC <- PC + 1

16-bit Opcode:

0000

0001

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

movw r17:16,r1:r0 ; Copy r1:r0 to r17:r16

call check ; Call subroutine

...

check: cpi r16,$11 ; Compare r16 to $11

...

cpi r17,$32 ; Compare r17 to $32

...

ret ; Return from subroutine

Words: 1 (2 bytes)

Cycles: 1


MUL - Multiply Unsigned

Description:

This instruction performs 8-bit × 8-bit → 16-bit unsigned multiplication.

Rd |  | Rr |  | R1 | R0
Multiplicand | × | Multiplier | -> | Product High | Product Low
8 |  | 8 |  | 16 |

The multiplicand Rd and the multiplier Rr are two registers containing unsigned numbers. The 16-bit unsigned product is placed in R1 (high byte) and R0 (low byte). Note that if the multiplicand or the multiplier is selected from R0 or R1 the result will overwrite those after multiplication.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) R1:R0 <- Rd × Rr(unsigned <- unsigned × unsigned)

Syntax:          Operands:                        Program Counter:

(i) MUL Rd,Rr    0 ≤ d ≤ 31, 0 ≤ r ≤ 31           PC ← PC + 1

16-bit Opcode:

1001

11rd

dddd

rrrr

Status Register (SREG) and Boolean Formulae:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | <> | <>

C: R15

Set if bit 15 of the result is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

mul r5,r4                 ; Multiply unsigned r5 and r4

movw r4,r0                ; Copy result back in r5:r4

Words: 1 (2 bytes)

Cycles: 2


MULS - Multiply Signed

Description:

This instruction performs 8-bit × 8-bit → 16-bit signed multiplication.

Rd |  | Rr |  | R1 | R0
Multiplicand | × | Multiplier | → | Product High | Product Low
8 |  | 8 |  | 16 |

The multiplicand Rd and the multiplier Rr are two registers containing signed numbers. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i)R1:R0 ← Rd × Rr(signed ← signed × signed)

Syntax:             Operands:                      Program Counter:

(i)MULS Rd,Rr       16 ≤ d ≤ 31, 16 ≤ r ≤ 31       PC ← PC + 1

16-bit Opcode:

0000

0010

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | ⇔ | ⇔

C: R15

Set if bit 15 of the result is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

muls r21,r20         ; Multiply signed r21 and r20

movw r20,r0          ; Copy result back in r21:r20

Words: 1 (2 bytes)

Cycles: 2


MULSU - Multiply Signed with Unsigned

Description:

This instruction performs 8-bit × 8-bit → 16-bit multiplication of a signed and an unsigned number.

Rd |  | Rr |  | R1 | R0
Multiplicand | × | Multiplier | → | Product High | Product Low
8 |  | 8 |  | 16 |

The multiplicand Rd and the multiplier Rr are two registers. The multiplicand Rd is a signed number, and the multiplier Rr is unsigned. The 16-bit signed product is placed in R1 (high byte) and R0 (low byte).

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) R1:R0 ← Rd × Rr(signed ← signed × unsigned)

Syntax:            Operands:                        Program Counter:

(i) MULSU Rd,R     r16 ≤ d ≤ 23, 16 ≤ r ≤ 23        PC ← PC + 1

16-bit Opcode:

0000

0011

0ddd

0rrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | ⇔ | ⇔

C: R15

Set if bit 15 of the result is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

R (Result) equals R1,R0 after the operation.

Example:

;******************************************************************************

;* DESCRIPTION

;*Signed multiply of two 16-bit numbers with 32-bit result.

;* USAGE

;*r19:r18:r17:r16 = r23:r22 * r21:r20

;******************************************************************************

muls16x16_32:

clr r2

muls r23, r21                 ; (signed)ah * (signed)bh

movw r19:r18, r1:r0

mul r22, r20; al * bl

movw r17:r16, r1:r0

mulsu r23, r20                ; (signed)ah * bl

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

mulsu r21, r22                ; (signed)bh * al

sbc r19, r2

add r17, r0

adc r18, r1

adc r19, r2

ret

Words: 1 (2 bytes)

Cycles: 2


NEG - Two's Complement

Description:

Replaces the contents of register Rd with its two's complement; the value $80 is left unchanged.

Operation:

(i)Rd ← $00 - Rd

Syntax:         Operands:                          Program Counter:

(i) NEG Rd      0 ≤ d ≤ 31                         PC ← PC + 1

16-bit Opcode:

1001

010d

dddd

0001

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H:R3 + Rd3

Set if there was a borrow from bit 3; cleared otherwise

S:N [+] V

For signed tests.

V:R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if there is a two's complement overflow from the implied subtraction from zero; cleared otherwise. A two's complement overflow will occur if and only if the contents of the Register after operation (Result) is $80.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; Cleared otherwise.

C:R7 + R6 + R5 + R4 + R3 + R2 + R1 + R0

Set if there is a borrow in the implied subtraction from zero; cleared otherwise. The C flag will be set in all cases except when the contents of Register after operation is $00.

R (Result) equals Rd after the operation.

Example:

sub r11,r0    ; Subtract r0 from r11

brpl positive ; Branch if result positive

neg r11       ; Take two's complement of r11

positive:  nop           ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


NOP - No Operation

Description:

This instruction performs a single cycle No Operation.

Operation:

(i)No

Syntax:         Operands:               Program Counter:

(i) NOP         None                    PC ← PC + 1

16-bit Opcode:

0000

0000

0000

0000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clrr16                  ; Clear r16

serr17                  ; Set r17

out$18,r16              ; Write zeros to Port B

nop                     ; Wait (do nothing)

out$18,r17              ; Write ones to Port B

Words: 1 (2 bytes)

Cycles: 1


OR - Logical OR

Description:

Performs the logical OR between the contents of register Rd and register Rr and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd v Rr

Syntax:Operands:Program Counter:

(i)OR Rd,Rr0 ≤ d ≤ 31, 0 ≤ r ≤ 31PC ← PC + 1

16-bit Opcode:

0010

10rd

dddd

rrrr

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N [+] V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

or r15,r16    ; Do bitwise or between registers

bst r15,6     ; Store bit 6 of r15 in T flag

brts ok       ; Branch if T flag set

...

ok:   nop           ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


ORI - Logical OR with Immediate

Description:

Performs the logical OR between the contents of register Rd and a constant and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd v K

Syntax:          Operands:                     Program Counter:

(i)ORI Rd,K      16 ≤ d ≤ 31, 0 ≤ K ≤ 255      PC ← PC + 1

16-bit Opcode:

0110

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N [+] V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

ori r16,$F0      ; Set high nibble of r16

ori r17,1        ; Set bit 0 of r17

Words: 1 (2 bytes)

Cycles: 1


OUT - Store Register to I/O Location

Description:

Stores data from register Rr in the register file to I/O Space (Ports, Timers, Configuration registers etc.).

Operation:

(i)I/O(A) ← Rr

Syntax:         Operands:                      Program Counter:

(i) OUT A,Rr    0 ≤ r ≤ 31, 0 ≤ A ≤ 63         PC ← PC + 1

16-bit Opcode:

1011

1AAr

rrrr

AAAA

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr r16         ; Clear r16

ser r17         ; Set r17

out $18,r16     ; Write zeros to Port B

nop             ; Wait (do nothing)

out $18,r17     ; Write ones to Port B

Words: 1 (2 bytes)

Cycles: 1


POP - Pop Register from Stack

Description:

This instruction loads register Rd with a byte from the STACK. The stack pointer is pre-incremented by 1 before the POP.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i)Rd ← STACK

Syntax:          Operands:                    Program Counter:           Stack:

(i) POP Rd       0 ≤ d ≤ 31                   PC ← PC + 1                SP ← SP + 1

16-bit Opcode:

1001

000d

dddd

1111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

callroutine               ; Call subroutine

...

routine:   pushr14        ; Save r14 on the stack

push r13       ; Save r13 on the stack

...

pop r13        ; Restore r13

pop r14        ; Restore r14

ret            ; Return from subroutine

Words: 1 (2 bytes)

Cycles: 2


PUSH - Push Register on Stack

Description:

This instruction stores the contents of register Rr on the STACK. The stack pointer is post-decremented by 1 after the PUSH.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i) STACK ← Rr

Syntax:          Operands:            Program Counter:             Stack:

(i) PUSH Rr      0 ≤ r ≤ 31           PC ← PC + 1                  SP ← SP - 1

16-bit Opcode:

1001

001d

dddd

1111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

callroutine           ; Call subroutine

...

routine:   push r14   ; Save r14 on the stack

push r13   ; Save r13 on the stack

...

pop r13    ; Restore r13

pop r14    ; Restore r14

ret        ; Return from subroutine

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega
PUSH | 2 | 1


RCALL - Relative Call to Subroutine

Description:

Relative call to an address within PC - 2K + 1 and PC + 2K (words). The return address (the instruction after the RCALL) is stored onto the stack. (See also CALL). In the assembler, labels are used instead of relative operands. For AVR microcontrollers with program memory not exceeding 4K words (8K bytes) this instruction can address the entire memory from every address location. The stack pointer uses a post-decrement scheme during RCALL.

Operation:

(i)PC ← PC + k + 1 Devices with 16 bits PC, 128K bytes program memory maximum.

(ii)PC ← PC + k + 1 Devices with 22 bits PC, 8M bytes program memory maximum.

Syntax:        Operands:                  Program Counter:             Stack:

(i) RCALL k    -2K ≤ k < 2K               PC ← PC + k + 1              STACK ← PC + 1

                                                                       SP ← SP - 2 (2 bytes, 16 bits)

(ii)RCALL k    -2K ≤ k < 2K               PC ← PC + k + 1              STACK ← PC + 1

                                                                       SP ← SP - 3 (3 bytes, 22 bits)

16-bit Opcode:

1101

kkkk

kkkk

kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

rcallroutine             ; Call subroutine

...

routine:    push r14     ; Save r14 on the stack

...

pop r14      ; Restore r14

ret          ; Return from subroutine

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
Devices with 16-bit PC | 3 | 2 | 4
Devices with 22-bit PC | 4 | 3 | N/A


RET - Return from Subroutine

Description:

Returns from subroutine. The return address is loaded from the STACK. The stack pointer uses a pre-increment scheme during RET.

Operation:

(i)PC(15:0) ← STACK Devices with 16 bits PC, 128K bytes program memory maximum.

(ii)PC(21:0) ← STACK Devices with 22 bits PC, 8M bytes program memory maximum.

Syntax:        Operands:                  Program Counter:             Stack:

(i) RET        None                       See Operation                SP←SP + 2, (2bytes,16 bits)

(ii) RET       None                       See Operation                SP←SP + 3, (3bytes,22 bits)

16-bit Opcode:

1001

0101

0000

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

callroutine                     ; Call subroutine

...

routine:   push r14             ; Save r14 on the stack

...

pop r14             ; Restore r14

ret                 ; Return from subroutine

Words: 1 (2 bytes)

Cycles: 4 devices with 16-bit PC

5 devices with 22-bit PC


RETI - Return from Interrupt

Description:

Returns from interrupt. The return address is loaded from the STACK and the global interrupt flag is set.

Note that the status register is not automatically stored when entering an interrupt routine, and it is not restored when returning from an interrupt routine. This must be handled by the application program. The stack pointer uses a pre-increment scheme during RETI.

Operation:

(i)PC(15:0) ← STACKDevices with 16 bits PC, 128K bytes program memory maximum.

(ii)PC(21:0) ← STACKDevices with 22 bits PC, 8M bytes program memory maximum.

Syntax:        Operands:                   Program Counter:            Stack

(i) RETI       None                        See Operation               SP ← SP + 2 (2 bytes, 16 bits)

(ii) RETI      None                        See Operation               SP ← SP + 3 (3 bytes, 22 bits)

16-bit Opcode:

1001

0101

0001

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
1 | - | - | - | - | - | - | -

I: 1

The I flag is set.

Example:

...

extint:    push     r0      ; Save r0 on the stack

...

pop     r0      ; Restore r0

reti            ; Return and enable interrupts

Words: 1 (2 bytes)

Cycles: 4 devices with 16-bit PC

5 devices with 22-bit PC


RJMP - Relative Jump

Description:

Relative jump to an address within PC - 2K +1 and PC + 2K (words). In the assembler, labels are used instead of relative operands. For AVR microcontrollers with program memory not exceeding 4K words (8K bytes) this instruction can address the entire memory from every address location.

Operation:

(i)PC ← PC + k + 1

Syntax:        Operands:             Program Counter:            Stack

(i) RJMP k     -2K ≤ k < 2K          PC ← PC + k + 1             Unchanged

16-bit Opcode:

1100

kkkk

kkkk

kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

cpir16,$42              ; Compare r16 to $42

brneerror               ; Branch if r16 <> $42

rjmpok                  ; Unconditional branch

error:addr16,r17              ; Add r17 to r16

incr16                  ; Increment r16

ok:   nop                     ; Destination for rjmp (do nothing)

Words: 1 (2 bytes)

Cycles: 2


ROL - Rotate Left trough Carry

Description:

Shifts all bits in Rd one place to the left. The C flag is shifted into bit 0 of Rd. Bit 7 is shifted into the C flag. This operation, combined with LSL, effectively multiplies multi-byte signed and unsigned values by two.

Operation:

C

¨

b7 ------------------b0

←

C

Syntax:         Operands:                     Program Counter:

(i)ROL Rd       0 ≤ d ≤ 31                    PC ← PC + 1

16-bit Opcode: (see ADC Rd,Rd)

0001

11dd

dddd

dddd

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H:Rd3

S: N [+] V, For signed tests.

V:N [+] C (For N and C after the shift)

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C:Rd7

Set if, before the shift, the MSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

lsl r18             ; Multiply r19:r18 by two

rol r19             ; r19:r18 is a signed or unsigned two-byte integer

brcsoneenc               ; Branch if carry set

...

oneenc:nop               ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


ROR - Rotate Right through Carry

Description:

Shifts all bits in Rd one place to the right. The C flag is shifted into bit 7 of Rd. Bit 0 is shifted into the C flag. This operation, combined with ASR, effectively divides multi-byte signed values by two. Combined with LSR it effectively divides multi-byte unsigned values by two. The carry flag can be used to round the result.

Operation:

C

→

b7------------------b0

→

C

Syntax:            Operands:                         Program Counter:

(i) ROR Rd         0 ≤ d ≤ 31                        PC ← PC + 1

16-bit Opcode:

1001

010d

dddd

0111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | <> | <> | <> | <>

S: N [+] V, For signed tests.

V:N [+] C (For N and C after the shift)

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C:Rd0

Set if, before the shift, the LSB of Rd was set; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

lsr r19                     ; Divide r19:r18 by two

ror r18                     ; r19:r18 is an unsigned two-byte integer

brcc zeroenc1               ; Branch if carry cleared

asr r17                     ; Divide r17:r16 by two

ror r16                     ; r17:r16 is a signed two-byte integer

brcc zeroenc2               ; Branch if carry cleared

...

zeroenc1:nop                     ; Branch destination (do nothing)

...

zeroenc2:nop                     ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


SBC - Subtract with Carry

Description:

Subtracts two registers and subtracts with the C flag and places the result in the destination register Rd.

Operation:

(i) Rd ← Rd - Rr - C

Syntax:          Operands:                        Program Counter:

(i) SBC Rd,Rr    0 ≤ d ≤ 31, 0 ≤ r ≤ 31           PC ← PC + 1

16-bit Opcode:

0000

10rd

dddd

rrrr

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • Rr3 + Rr3 • R3 + R3 • Rd3

Set if there was a borrow from bit 3; cleared otherwise

S: N [+] V, For signed tests.

V:Rd7 • Rr7 • R7 + Rd7 • Rr7 • R7

Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 • Z

Previous value remains unchanged when the result is zero; cleared otherwise.

C: Rd7 • Rr7+ Rr7 • R7 +R7 • Rd7

Set if the absolute value of the contents of Rr plus previous carry is larger than the absolute value of the Rd; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

                ; Subtract r1:r0 from r3:r2

sub r2,r0       ; Subtract low byte

sbc r3,r1       ; Subtract with carry high byte

Words: 1 (2 bytes)

Cycles: 1


SBR - Set Bits in Register

Description:

Sets specified bits in register Rd. Performs the logical ORI between the contents of register Rd and constant mask K and places the result in the destination register Rd.

Operation:

(i)Rd <- Rd v K

Syntax:               Operands:                        Program Counter:

(i)SBR Rd,K           16<=d<=31, 0<=K<=255             PC ← PC + 1

16-bit Opcode:

0110

KKKK

dddd

KKKK

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N ⊕ V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: 'R7 • 'R6 • 'R5 • 'R4 • 'R3 • 'R2 • 'R1 • 'R0

R (Result) equals Rd after the operation.

Example:

sbr   r16,3      ; Set bits 0 and 1 in r16

sbr   r17,$F0    ; Set 4 MSB in r17

Words: 1 (2 bytes)

Cycles: 1


SBRC - Skip if Bit in Register is Cleared

Description:

This instruction tests a single bit in a register and skips the next instruction if the bit is cleared.

Operation:

(i)If Rr(b) = 0 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax:        Operands:                    Program Counter:

(i)SBRC Rr,b   0 ≤ r ≤ 31, 0 ≤ b ≤ 7        PC ← PC + 1, Condition false - no skip

                                            PC ← PC + 2, Skip a one word instruction

                                            PC ← PC + 3, Skip a two word instruction

16-bit Opcode:

1111

110r

rrrr

0bbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

sub r0,r1            ; Subtract r1 from r0

sbrc r0,7            ; Skip if bit 7 in r0 cleared

sub r0,r1            ; Only executed if bit 7 in r0 not cleared

nop                  ; Continue (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false (no skip)

2 if condition is true (skip is executed) and the instruction skipped is 1 word

3 if condition is true (skip is executed) and the instruction skipped is 2 words


SBRS - Skip if Bit in Register is Set

Description:

This instruction tests a single bit in a register and skips the next instruction if the bit is set.

Operation:

(i)If Rr(b) = 1 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax:        Operands:                      Program Counter:

(i)SBRS Rr,b   0 ≤ r ≤ 31, 0 ≤ b ≤ 7          PC ← PC + 1, Condition false - no skip

                                              PC ← PC + 2, Skip a one word instruction

                                              PC ← PC + 3, Skip a two word instruction

16-bit Opcode:

1111

111r

rrrr

0bbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

sub   r0,r1   ; Subtract r1 from r0

sbrs  r0,7    ; Skip if bit 7 in r0 set

neg   r0      ; Only executed if bit 7 in r0 not set

nop           ; Continue (do nothing)

Words: 1 (2 bytes)

Cycles: 1 if condition is false (no skip)

2 if condition is true (skip is executed) and the instruction skipped is 1 word

3 if condition is true (skip is executed) and the instruction skipped is 2 words


SEC - Set Carry Flag

Description:

Sets the Carry flag (C) in SREG (status register).

Operation:

(i)C ← 1

Syntax:         Operands:                    Program Counter:

(i)SEC          None                         PC ← PC + 1

16-bit Opcode:

1001

0100

0000

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | 1

C: 1

Carry flag set

Example:

sec          ; Set carry flag

adc r0,r1    ; r0=r0+r1+1

Words: 1 (2 bytes)

Cycles: 1


SEH - Set Half Carry Flag

Description:

Sets the Half Carry (H) in SREG (status register).

Operation:

(i)H ← 1

Syntax:            Operands:               Program Counter:

(i) SEH            None                    PC ← PC + 1

16-bit Opcode:

1001

0100

0101

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | 1 | - | - | - | - | -

H: 1

Half Carry flag set

Example:

seh ; Set Half Carry flag

Words: 1 (2 bytes)

Cycles: 1


SBI - Set Bit in I/O Register

Description:

Sets a specified bit in an I/O register. This instruction operates on the lower 32 I/O registers - addresses 0-31.

Operation:

(i)I/O(A,b) ← 1

Syntax:        Operands:              Program Counter:

(i)SBI A,b     0 ≤ A ≤ 31, 0 ≤ b ≤ 7  PC ← PC + 1

16-bit Opcode:

1001

1010

AAAA

Abbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

out  $1E,r0   ; Write EEPROM address

sbi  $1C,0    ; Set read bit in EECR

in   r1,$1D   ; Read EEPROM data

Words: 1 (2 bytes)

Cycles: 2
Cycles xmega/AVR8L: 1


SBCI - Subtract Immediate with Carry

Description:

Subtracts a constant from a register and subtracts with the C flag and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd - K - C

Syntax:         Operands:                      Program Counter:

(i) SBCI Rd,K   16 ≤ d ≤ 31, 0 ≤ K ≤ 255       PC ← PC + 1

16-bit Opcode:

0100

KKKK

dddd

KKKK

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • K3 + K3 • R3 + R3 • Rd3

Set if there was a borrow from bit 3; cleared otherwise

S: N [+] V, For signed tests.

V:Rd7 • K7 • R7 + Rd7 • K7 • R7

Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0 • Z

Previous value remains unchanged when the result is zero; cleared otherwise.

C: Rd7 • K7+ K7 • R7 +R7 • Rd7

Set if the absolute value of the constant plus previous carry is larger than the absolute value of Rd; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

; Subtract $4F23 from r17:r16

subi   r16,$23   ; Subtract low byte

sbci  r17,$4F    ; Subtract with carry high byte

Words: 1 (2 bytes)

Cycles: 1


SBIC - Skip if Bit in I/O Register is Cleared

Description:

This instruction tests a single bit in an I/O register and skips the next instruction if the bit is cleared. This instruction operates on the lower 32 I/O registers - addresses 0-31.

Operation:

(i)If I/O(A,b) = 0 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax:         Operands:                       Program Counter:

(i)SBIC A,b     0 ≤ A ≤ 31, 0 ≤ b ≤ 7           PC ← PC + 1, Condition false - no skip

                                                PC ← PC + 2, Skip a one word instruction

                                                PC ← PC + 3, Skip a two word instruction

16-bit Opcode:

1001

1001

AAAA

Abbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

e2wait:    sbic$1C,1               ; Skip next inst. if EEWE cleared

rjmp e2wait             ; EEPROM write not finished

nop; Continue (do nothing)

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
Condition is false | 1 | 2 | 1
Condition is true and instruction skipped is 1 word | 2 | 3 | 2
Condition is true and instruction skipped is 2 words | 3 | 4 | N/A


SBIS - Skip if Bit in I/O Register is Set

Description:

This instruction tests a single bit in an I/O register and skips the next instruction if the bit is set. This instruction operates on the lower 32 I/O registers - addresses 0-31.

Operation:

(i)If I/O(A,b) = 1 then PC ← PC + 2 (or 3) else PC ← PC + 1

Syntax:        Operands:                 Program Counter:

(i)SBIS A,b    0 ≤ A ≤ 31, 0 ≤ b ≤ 7     PC ← PC + 1, Condition false - no skip

                                         PC ← PC + 2, Skip a one word instruction

                                         PC ← PC + 3, Skip a two word instruction

16-bit Opcode:

1001

1011

AAAA

Abbb

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

waitset:   sbis $10,0        ; Skip next inst. if bit 0 in Port D set

rjmp waitset     ; Bit not set

nop              ; Continue (do nothing)

Words: 1 (2 bytes)

 | Cycles | Cycles xmega | Cycles AVR8L
Condition is false | 1 | 2 | 1
Condition is true and instruction skipped is 1 word | 2 | 3 | 2
Condition is true and instruction skipped is 2 words | 3 | 4 | N/A


SBIW - Subtract Immediate from Word

Description:

Subtracts an immediate value (0-63) from a register pair and places the result in the register pair. This instruction operates on the upper four register pairs, and is well suited for operations on the pointer registers.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Operation:

(i)Rd+1:Rd ← Rd+1:Rd - K

Syntax:               Operands:                        Program Counter:

(i)SBIW Rd+1:Rd,K     d E {24,26,28,30}, 0 ≤ K ≤ 63    PC ← PC + 1

16-bit Opcode:

1001

0111

KKdd

KKKK

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | ⇔ | ⇔ | ⇔ | ⇔ | ⇔

S: N ⊕ V, For signed tests.

V:Rdh7 • R15

Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R15

Set if MSB of the result is set; cleared otherwise.

Z: R15 • R14 • R13 • R12 • R11 • R10 • R9 • R8 • R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $0000; cleared otherwise.

C:R15 • Rdh7

Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

R (Result) equals Rdh:Rdl after the operation (Rdh7-Rdh0 = R15-R8, Rdl7-Rdl0=R7-R0).

Example:

sbiw r25:r24,1 ; Subtract 1 from r25:r24

sbiw YH:YL,63  ; Subtract 63 from the Y pointer(r29:r28)

Words: 1 (2 bytes)

Cycles: 2


SEI - Set Global Interrupt Flag

Description:

Sets the Global Interrupt flag (I) in SREG (status register). The instruction following SEI will be executed before any pending interrupts.

Operation:

(i) I ← 1

Syntax:        Operands:                     Program Counter:

(i) SEI        None                          PC ← PC + 1

16-bit Opcode:

1001

0100

0111

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
1 | - | - | - | - | - | - | -

I: 1

Global Interrupt flag set

Example:

sei ; set global interrupt enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

Words: 1 (2 bytes)

Cycles: 1


SEN - Set Negative Flag

Description:

Sets the Negative flag (N) in SREG (status register).

Operation:

(i) N ← 1

Syntax:         Operands:                  Program Counter:

(i) SEN         None                       PC ← PC + 1

16-bit Opcode:

1001

0100

0010

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | 1 | - | -

N: 1

Negative flag set

Example:

add r2,r19       ; Add r19 to r2

sen              ; Set negative flag

Words: 1 (2 bytes)

Cycles: 1


SER - Set all bits in Register

Description:

Loads $FF directly to register Rd.

Operation:

(i) Rd ← $FF

Syntax:            Operands:                    Program Counter:

(i) SER Rd         16 ≤ d ≤ 31                  PC ← PC + 1

16-bit Opcode:

1110

1111

dddd

1111

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr r16                 ; Clear r16

ser r17                 ; Set r17

out $18,r16             ; Write zeros to Port B

nop                     ; Delay (do nothing)

out $18,r17             ; Write ones to Port B

Words: 1 (2 bytes)

Cycles: 1


SES - Set Signed Flag

Description:

Sets the Signed flag (S) in SREG (status register).

Operation:

(i) S ← 1

Syntax:         Operands:                      Program Counter:

(i) SES         None                           PC ← PC + 1

16-bit Opcode:

1001

0100

0100

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | 1 | - | - | - | -

S: 1

Signed flag set

Example:

add r2,r19       ; Add r19 to r2

ses              ; Set negative flag

Words: 1 (2 bytes)

Cycles: 1


SET - Set T Flag

Description:

Sets the T flag in SREG (status register).

Operation:

(i) T ← 1

Syntax:         Operands:                        Program Counter:

(i) SET         None                             PC ← PC + 1

16-bit Opcode:

1001

0100

0110

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | 1 | - | - | - | - | - | -

T: 1

T flag set

Example:

set ; Set T flag

Words: 1 (2 bytes)

Cycles: 1


SEV - Set Overflow Flag

Description:

Sets the Overflow flag (V) in SREG (status register).

Operation:

(i) V ← 1

Syntax:            Operands:               Program Counter:

(i)SEV             None                    PC ← PC + 1

16-bit Opcode:

1001

0100

0011

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | 1 | - | - | -

V: 1

Overflow flag set

Example:

add r2,r19; Add r19 to r2

sev ; Set overflow flag

Words: 1 (2 bytes)

Cycles: 1


SEZ - Set Zero Flag

Description:

Sets the Zero flag (Z) in SREG (status register).

Operation:

(i) Z ← 1

Syntax:            Operands:                     Program Counter:

(i) SEZ            None                          PC ← PC + 1

16-bit Opcode:

1001

0100

0001

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | 1 | -

Z: 1

Zero flag set

Example:

add r2,r19     ; Add r19 to r2

sez            ; Set zero flag

Words: 1 (2 bytes)

Cycles: 1


SLEEP

Description:

This instruction sets the circuit in sleep mode defined by the MCU control register.

Operation:

Refer to the device documentation for detailed description of SLEEP usage.

Syntax:          Operands:                Program Counter:

SLEEP            None                     PC ← PC + 1

16-bit Opcode:

1001

0101

1000

1000

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

mov r0,r11            ; Copy r11 to r0

ldi r16,(1<<SE)       ; Enable sleep mode

out MCUCR, r16

sleep                 ; Put MCU in sleep mode

Words: 1 (2 bytes)

Cycles: 1


SPM - Store Program Memory

Description:

SPM can be used to erase a page in the program memory, to write a page in the program memory (that is already erased), and to set boot loader lock bits. In some devices, the program memory can be written one word at a time, in other devices an entire page can be programmed simultaneously after first filling a temporary page buffer. In all cases, the program memory must be erased one page at a time. When erasing the program memory, the RAMPZ and Z register are used as page address. When writing the program memory, the RAMPZ and Z register are used as page or word address, and the R1:R0 register pair is used as data. R1 determines the instruction high byte, and R0 determines the instruction low byte... When setting the boot loader lock bits, the R1:R0 register pair is used as data. Refer to the device documentation for detailed description of SPM usage. This instruction can address the entire program memory.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

  1. R1 determines the instruction high byte, and R0 determines the instruction low byte.

Operation:                             Comment:

(i)(RAMPZ:Z) ← $ffff                   Erase program memory pagerns21i

(ii)(RAMPZ:Z) ← R1:R0                  Write program memory word

(iii)(RAMPZ:Z) ← R1:R0                 Write temporary page buffer

(iv)(RAMPZ:Z) ← TEMP                   Write temporary page buffer to program memory

(v)BLBITS ← R1:R0                      Set boot loader lock bits

Syntax:         Operands:              Program Counter:

(i)-(v) SPM     None                   PC ← PC + 1

16-bit Opcode:

1001

0101

1110

1000

Status Register (SREG) and Boolean Formula:

I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

;This example shows SPM write of one page for devices with page write

;- the routine writes one page of data from RAM to Flash

; the first data location in RAM is pointed to by the Y pointer

; the first data location in Flash is pointed to by the Z pointer

;- error handling is not included

;- the routine must be placed inside the boot space

; (at least the do_spm sub routine)

;- registers used: r0, r1, temp1, temp2, looplo, loophi, spmcrval

; (temp1, temp2, looplo, loophi, spmcrval must be defined by the user)

; storing and restoring of registers is not included in the routine

; register usage can be optimized at the expense of code size

.equ PAGESIZEB = PAGESIZE*2;PAGESIZEB is page size in BYTES, not words

.org SMALLBOOTSTART

write_page:

;page erase

ldi spmcrval, (1<<PGERS) + (1<<SPMEN)

call do_spm

;transfer data from RAM to Flash page buffer

ldi looplo, low(PAGESIZEB)              ;init loop variable

ldi loophi, high(PAGESIZEB)             ;not required for PAGESIZEB<=256

wrloop:ld r0, Y+

ld r1, Y+

ldi spmcrval, (1<<SPMEN)

call do_spm

adiw ZH:ZL, 2

sbiw loophi:looplo, 2;use subi for PAGESIZEB<=256

brne wrloop

;execute page write

subi ZL, low(PAGESIZEB)                 ;restore pointer

sbci ZH, high(PAGESIZEB)                ;not required for PAGESIZEB<=256

ldi spmcrval, (1<<PGWRT) + (1<<SPMEN)

call do_spm

;read back and check, optional

ldi looplo, low(PAGESIZEB)              ;init loop variable

ldi loophi, high(PAGESIZEB)             ;not required for PAGESIZEB<=256

subi YL, low(PAGESIZEB)                 ;restore pointer

sbci YH, high(PAGESIZEB)

rdloop:lpmr0, Z+

ldr 1, Y+

cp ser0, r1

jmp error

sbi wloophi:looplo, 2;use subi for PAGESIZEB<=256

brne rdloop

;return

ret

do_spm:

;input: spmcrval determines SPM action

;disable interrupts if enabled, store status

in temp2, SREG

cli

;check for previous SPM complete

wait:intemp1, SPMCR

sbr ctemp1, SPMEN

rjm pwait

;SPM timed sequence

out SPMCR, spmcrval

spm

;restore SREG (to enable interrupts if originally enabled)

out SREG, temp2

ret

Words: 1 (2 bytes)

Cycles: depends on the operation


SPM #2

SPM #2– Store Program Memory

Description:

SPM can be used to erase a page in the Program memory and to write a page in the Program memory (that is already erased). An entire page can be programmed simultaneously after first filling a temporary page buffer. The Program memory must be erased one page at a time. When erasing the Program memory, the RAMPZ and Z-register are used as page address. When writing the Program memory, the RAMPZ and Z-register are used as page or word address, and the R1:R0 register pair is used as data(1).

Refer to the device documentation for detailed description of SPM usage. This instruction can address the entire Program memory.

This instruction is not available in all devices. Refer to the device specific instruction set summary.

Note: 1. R1 determines the instruction high byte, and R0 determines the instruction low byte.

Operation: Comment:
(i) (RAMPZ:Z) <- $ffff Erase Program memory page
(ii) (RAMPZ:Z) <- R1:R0 Load Page Buffer
(iii)(RAMPZ:Z) <- BUFFER Write Page Buffer to Program memory
(iv) (RAMPZ:Z) <- $fff Z <- Z+2 Erase Program memory page, Z post incremented
(v) (RAMPZ:Z) <- R1:R0 Z <- Z+2 Load Page Buffer, Z post incremented
(vi) (RAMPZ:Z) <- BUFFER Z <- Z+2 Write Page Buffer to Program memory, Z post incremented

Syntax: Operands: Program Counter:
(i)-(iii) SPM None PC <- PC + 1
(iv)-(vi) SPM Z+ None PC <- PC + 1

16-bit Opcode:

(i)-(iii) 1001 0101 1110 1000
(iv)-(vi) 1001 0101 1111 1000

Status Register (SREG) and Boolean Formula:

I T H S V N Z C
– – – – – – – –

Example:

TBD

Words: 1 (2 bytes)

Cycles: depends on the operation


ST - Store Indirect From Register to data space using Index X

Description:

Stores one byte indirect from a register to data space. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

The data location is pointed to by the X (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPX in register in the I/O area has to be changed.

The X pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the X pointer register. Note that only the low byte of the X pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPX register in the I/O area is updated in parts with more than 64K bytes data space or more than 64K bytes program memory, and the increment/ decrement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

The result of these combinations is undefined:

ST X+, r26

ST X+, r27

ST -X, r26

ST -X, r27

Using the X pointer:

Operation:                                  Comment:

(i)(X) ← Rr                                 X: Unchanged

(ii)(X) ← Rr         X ← X+1                X: Post incremented

(iii)X ← X - 1       (X) ← Rr               X: Pre decremented

Syntax:              Operands:              Program Counter:

(i)ST X, Rr          0 ≤ r ≤ 31             PC ← PC + 1

(ii)ST X+, Rr        0 ≤ r ≤ 31             PC ← PC + 1

(iii)ST -X, Rr       0 ≤ r ≤ 31             PC ← PC + 1

16-bit Opcode :

(i) | 1001 | 001r | rrrr | 1100
(ii) | 1001 | 001r | rrrr | 1101
(iii) | 1001 | 001r | rrrr | 1110

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr   r27            ; Clear X high byte

ldi   r26,$60        ; Set X low byte to $60

st    X+,r0          ; Store r0 in data space loc. $60(X post inc)

st    X,r1           ; Store r1 in data space loc. $61

ldi   r26,$63        ; Set X low byte to $63

st    X,r2           ; Store r2 in data space loc. $63

st   -X,r3           ; Store r3 in data space loc. $62(X pre dec)

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
(i) | 2 | 1 | 1
(ii) | 2 | 1 | 1
(iii) | 2 | 2 | 2


ST (STD) - Store Indirect From Register to data space using Index Y

Description:

Stores one byte indirect with or without displacement from a register to data space. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

The data location is pointed to by the Y (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPY in register in the I/O area has to be changed.

The Y pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for accessing arrays, tables, and stack pointer usage of the Y pointer register. Note that only the low byte of the Y pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPY register in the I/O area is updated in parts with more than 64K bytes data space or more than 64K bytes program memory, and the increment/ decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

The result of these combinations is undefined:

ST Y+, r28

ST Y+, r29

ST -Y, r28

ST -Y, r29

Using the Y pointer:

Operation:                                                 Comment:

(i)    (Y) ← Rr                                            Y: Unchanged

(ii)   (Y) ← Rr                Y ← Y+1                     Y: Post incremented

(iii)   Y ← Y - 1              (Y) ← Rr                    Y: Pre decremented

(iiii)* (Y+q) ← Rr                                         Y: Unchanged, q: Displacement

Syntax:                     Operands:                     Program Counter:

(i)     ST Y, Rr            0 ≤ r ≤ 31                    PC ← PC + 1

(ii)    ST Y+, Rr           0 ≤ r ≤ 31                    PC ← PC + 1

(iii)   ST -Y, Rr           0 ≤ r ≤ 31                    PC ← PC + 1

(iiii)* STD Y+q, Rr         0 ≤ r ≤ 31, 0 ≤ q ≤ 63        PC ← PC + 1

Notes:

*) The displacement form of this instruction (LDD) is not available on AVR8L based devices.

16-bit Opcode:

(i) | 1000 | 001r | rrrr | 1000
(ii) | 1001 | 001r | rrrr | 1001
(iii) | 1001 | 001r | rrrr | 1010
(iiii) | 10q0 | qq1r | rrrr | 1qqq

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr        r29               ; Clear Y high byte

ldi        r28,$60           ; Set Y low byte to $60

st         Y+,r0             ; Store r0 in data space loc. $60(Y post inc)

st         Y,r1              ; Store r1 in data space loc. $61

ldi        r28,$63           ; Set Y low byte to $63

st         Y,r2              ; Store r2 in data space loc. $63

st         -Y,r3             ; Store r3 in data space loc. $62(Y pre dec)

std        Y+2,r4            ; Store r4 in data space loc. $64

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
(i) | 2 | 1 | 1
(ii) | 2 | 1 | 1
(iii) | 2 | 2 | 2
(iiii) | 2 | 2 | N/A


ST (STD) - Store Indirect From Register to data space using Index Z

Description:

Stores one byte indirect with or without displacement from a register to data space. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

The data location is pointed to by the Z (16 bits) pointer register in the register file. Memory access is limited to the current data segment of 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPZ in register in the I/O area has to be changed.

The Z pointer register can either be left unchanged by the operation, or it can be post-incremented or pre-decremented. These features are especially suited for stack pointer usage of the Z pointer register, however because the Z pointer register can be used for indirect subroutine calls, indirect jumps and table lookup, it is often more convenient to use the X or Y pointer as a dedicated stack pointer. Note that only the low byte of the Z pointer is updated in devices with no more than 256 bytes data space. For such devices, the high byte of the pointer is not used by this instruction and can be used for other purposes. The RAMPZ register in the I/O area is updated in parts with more than 64K bytes data space or more than 64K bytes program memory, and the increment/decrement/displacement is added to the entire 24-bit address on such devices.

Not all variants of this instruction is available in all devices. Refer to the device specific instruction set summary.

The result of these combinations is undefined:

ST Z+, r30

ST Z+, r31

ST -Z, r30

ST -Z, r31

Using the Z pointer:

Operation:                                                          Comment:

(i)     (Z) ←Rr                                                     Z: Unchanged

(ii)    (Z) ← Rr                 Z ← Z+1                            Z: Post incremented

(iii)    Z ← Z - 1               (Z) ← Rr                           Z: Pre decremented

(iiii)*  (Z+q) ← Rr                                                 Z: Unchanged, q: Displacement

Syntax:                          Operands:                          Program Counter:

(i)     ST Z, Rr                 0 ≤ r ≤ 31                         PC ← PC + 1

(ii)    ST Z+, Rr                0 ≤ r ≤ 31                         PC ← PC + 1

(iii)   ST -Z, Rr                0 ≤ r ≤ 31                         PC ← PC + 1

(iiii)* STD Z+q, Rr              0 ≤ r ≤ 31, 0 ≤ q ≤ 63             PC ← PC + 1

Notes:

*) The displacement form of this instruction (LDD) is not available on AVR8L based devices.

16-bit Opcode :

(i) | 1000 | 001r | rrrr | 0000
(ii) | 1001 | 001r | rrrr | 0001
(iii) | 1001 | 001r | rrrr | 0010
(iiii) | 10q0 | qq1r | rrrr | 0qqq
Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

clr          r31                 ; Clear Z high byte

ldi          r30,$60             ; Set Z low byte to $60

st           Z+,r0               ; Store r0 in data space loc. $60(Z post inc)

st           Z,r1                ; Store r1 in data space loc. $61

ldi          r30,$63             ; Set Z low byte to $63

st           Z,r2                ; Store r2 in data space loc. $63

st           -Z,r3               ; Store r3 in data space loc. $62(Z pre dec)

std          Z+2,r4              ; Store r4 in data space loc. $64

Words: 1 (2 bytes)

Cycles:

 | Cycles | Cycles xmega | Cycles AVR8L
(i) | 2 | 1 | 1
(ii) | 2 | 1 | 1
(iii) | 2 | 2 | 2
(iiii) | 2 | 2 | N/A


STS - Store Direct to data space

Description:

Stores one byte from a Register to the data space. For parts with SRAM, the data space consists of the register file, I/O memory and internal SRAM (and external SRAM if applicable). For parts without SRAM, the data space consists of the register file only. The EEPROM has a separate address space.

A 16-bit address must be supplied. Memory access is limited to the current data segment of 64K bytes. The STS instruction uses the RAMPD register to access memory above 64K bytes. To access another data segment in devices with more than 64K bytes data space, the RAMPD in register in the I/O area has to be changed.

This instruction is not available in all devices. Refer to the device specific instruction set summary. In particular, notice that AVR8L-based devices use the 1-word STS instruction instead of this instruction.

Operation:

(i)(k) ← Rr

Syntax:              Operands:                      Program Counter:

(i)STS k,Rr          0 ≤ r ≤ 31, 0 ≤ k ≤ 65535      PC ← PC + 2

32-bit Opcode:

1001 | 001d | dddd | 0000
kkkk | kkkk | kkkk | kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

lds     r2,$FF00    ; Load r2 with the contents of data space location $FF00

add     r2,r1       ; add r1 to r2

sts     $FF00,r2    ; Write back

Words: 2 (4 bytes)

Cycles: 2


STS - Store Direct to SRAM

This 1-word form of the STS instruction is only used on AVR8L-based devices. Other AVR devices use the 2-word STS instruction.

Stores one byte from a register to the SRAM section of the data space.

An 8-bit address in the range 0x40 <= k <= 0xBF must be supplied. The assembler will calculate an 7-bit offset into the SRAM memory from this address, hence this instruction is capable of addressing up to 128 bytes of SRAM. This instruction cannot be used to store I/O addresses, use the OUT instruction for this purpose.

Operation:

(i)(k) <- Rr

Syntax:               Operands:                            Program Counter:

(i)STS k, Rr          16 ≤ r ≤ 31, 0x40 ≤ k ≤ 0xBF         PC <- PC + 1

16-bit Opcode:

1010

1kkk

rrrr

kkkk

Status Register (SREG) and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

lds r16,$40 ; Load r16 with the contents of data space location $FF00

add r16,r17 ; add r17 to r16

sts $40,r16 ; Write back

Words: 1 (2 bytes)

Cycles: 1


SUB - Subtract without Carry

Description:

Subtracts two registers and places the result in the destination register Rd.

Operation:

(i)Rd ← Rd - Rr

Syntax:          Operands:                  Program Counter:

(i)SUB Rd,Rr     0 ≤ d ≤ 31, 0 ≤ r ≤ 31     PC ← PC + 1

16-bit Opcode:

0001

10rd

dddd

rrrr

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • Rr3 +Rr3 • R3 +R3 • Rd3

Set if there was a borrow from bit 3; cleared otherwise

S: N ⊕ V, For signed tests.

V:Rd7 • Rr7 • R7 + Rd7 • Rr7 • R7

Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C: Rd7 • Rr7 +Rr7 • R7 +R7 • Rd7

Set if the absolute value of the contents of Rr is larger than the absolute value of Rd; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

sub      r13,r12       ; Subtract r12 from r13

brne     noteq         ; Branch if r12<>r13

...

noteq:     nop                    ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


SUBI - Subtract Immediate

Description:

Subtracts a register and a constant and places the result in the destination register Rd. This instruction is working on Register R16 to R31 and is very well suited for operations on the X, Y and Z pointers.

Operation:

(i)Rd ← Rd - K

Syntax:       Operands:                      Program Counter:

(i)SUBI Rd,K  16 ≤ d ≤ 31, 0 ≤ K ≤ 255       PC ← PC + 1

16-bit Opcode:

0101

KKKK

dddd

KKKK

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | <> | <> | <> | <> | <> | <>

H: Rd3 • K3+K3 • R3 +R3 • Rd3

Set if there was a borrow from bit 3; cleared otherwise

S: N [+] V, For signed tests.

V:Rd7 • K7 • R7 + Rd7 • K7 • R7

Set if two's complement overflow resulted from the operation; cleared otherwise.

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

C: Rd7 • K7 +K7 • R7 +R7 • Rd7

Set if the absolute value of K is larger than the absolute value of Rd; cleared otherwise.

R (Result) equals Rd after the operation.

Example:

subi    r22,$11       ; Subtract $11 from r22

brne    noteq         ; Branch if r22<>$11

...

noteq:     nop                   ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


SWAP - Swap Nibbles

Description:

Swaps high and low nibbles in a register.

Operation:

(i)R(7:4) ← Rd(3:0), R(3:0) ← Rd(7:4)

Syntax:             Operands:                          Program Counter:

(i)SWAP Rd          0 ≤ d ≤ 31                         PC ← PC + 1

16-bit Opcode:

1001

010d

dddd

0010

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

R (Result) equals Rd after the operation.

Example:

inc      r1             ; Increment r1

swap     r1             ; Swap high and low nibble of r1

inc      r1             ; Increment high nibble of r1

swap     r1             ; Swap back

Words: 1 (2 bytes)

Cycles: 1


TST - Test for Zero or Minus

Description:

Tests if a register is zero or negative. Performs a logical AND between a register and itself. The register will remain unchanged.

Operation:

(i)Rd ← Rd • Rd

Syntax:            Operands:                          Program Counter:

(i)TST Rd          0 ≤ d ≤ 31                         PC ← PC + 1

16-bit Opcode: (see AND Rd, Rd)

0010

00dd

dddd

dddd

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | <> | 0 | <> | <> | -

S: N [+] V, For signed tests.

V:0

Cleared

N:R7

Set if MSB of the result is set; cleared otherwise.

Z: R7 • R6 • R5 • R4 • R3 • R2 • R1 • R0

Set if the result is $00; cleared otherwise.

R (Result) equals Rd.

Example:

tst r0                     ; Test r0

breq zero                  ; Branch if r0=0

...

zero:      nop                         ; Branch destination (do nothing)

Words: 1 (2 bytes)

Cycles: 1


WDR - Watchdog Reset

Description:

This instruction resets the Watchdog Timer. This instruction must be executed within a limited time given by the WD prescaler. See the Watchdog Timer hardware specification.

Operation:

(i)WD timer restart.

Syntax:            Operands:                      Program Counter:

(i)WDR             None                           PC ← PC + 1

16-bit Opcode:

1001

0101

1010

1000

Status Register and Boolean Formula:
I | T | H | S | V | N | Z | C
- | - | - | - | - | - | - | -

Example:

wdr ; Reset watchdog timer

Words: 1 (2 bytes)

Cycles: 1


Known Issues

Common assembler project issues

The following is common for all AVR Assembler projects, regardless of the assembler version used.

  • Use of non-ASCII characters (like øåäè€) in project names, directory names, or source file names is not supported. The full pathname down to the project directory must consist of ASCII characters only. AVR Studio will allow the create projects with these characters, but building will fail.

AVR Assembler 2 Known Issues

AVR Assembler 1

Note that AVR Assembler 1 is obsoleted, these issues are not likely to be fixed. None of them are an issue in AVRASM2. New AVR devices introduced after AVR Studio 4.11 are NOT supported. AVR Assembler 1 should NOT be used in new projects.

The following list applies to AVRASM V1.77. Earlier versions may have more issues.

  • Some syntax errors are not detected by the parser. For instance, the conditional .if A = 0 is incorrect (the correct syntax is .if A == 0). Not only is this error undetected, but the assembler evaluates the statement as .if A which is the exact opposite of what was intended in this example. In some cases such errors have gone undetected until the program is assembled with AVRASM2.

  • Assembler will not detect improperly formatted numbers. Example:
    .def FOO = 3F
    will not produce an error message, and FOO gets the value 3. (the correct syntax is .def FOO = 0x3f or .def FOO = $3F

  • The characters '#' and ';' are taken as comment delimiters even when appearing in quotes, causing their use in strings ("#") or character constants (';') to produce "garbage at and of line" errors.

  • In a macro definition, the .endmacro directive must appear on a separate line, not at the same line as a label.

    label: .endmacro
    will produce an incorrect error message: "Macro call within macro not supported".

    The work-around is to split the line, i.e.:

    label:
    .endmacro

  • The assembler does not detect misplaced .elif conditionals in sequences like .if ... .else ... .elif ... .endif.

    Example: the following program will assemble without errors, and output the message "a != 1 && a != 0".

    .equ a = 0
    .if a == 1
    .message "a = 1"
    .else
    .message "a != 1 && a != 0"
    .elif a == 0
    .message "a = 0"
    .endif

  • The assembler does not support Motorola Hex output format for addresses > 0x10000 (64kB). Addresses > 0x10000 should be encoded as 3-byte S2 records but are incorrectly encoded as 2-byte S1 records - no warning is issued.

  • Maximum size of an assembler label is 31 chars. If the size extends this maximum, an error message will be given.


AVR Assembler 2

Atmel AVR Assembler 2

Starting with AVR Studio v. 4.11, AVR Assembler 2 (AVRASM2) is the default AVR assembler. It is a backward compatible replacement for AVRASM with many new features. The old assembler is still distributed with AVR Studio, but no longer maintained (i.e., new parts will no longer be supported by the old assembler).

AVRASM2 Topics

What's New - Introduction to AVRASM2 new features
AVR Assembler 2 Syntax
AVR Assembler 2 Preprocessor
AVR Assembler 2 Command Line Options
AVR Assembler 2 Known Issues


AVR Assembler 2 - What's New

AVRASM 2.1 is now released. Refer to the changelog below for a summary of changes from the previous release.

AVRASM2 Changelog

Changes between Assembler 1 and Assembler 2
C-style Preprocessor
Tightened Syntax
New assembler directives
Improved expression evaluation
Built-in "known place" for included files
Motorola hex for large files
Macro improvements

AVRASM2 Changelog

This changelog identifies major changes made in each AVRASM2 release.

Changes in 2.1.42 released with AVR Studio 4.18

  • STS/LDS instructions cause error when case sensitivity is enabled (#10246)

Changes in 2.1.30 released with AVR Studio 4.15

  • Support the new ATtiny10 instruction set. (#8359)

  • Fixed newline format in list files (#8069)

Changes in 2.1.17 released with AVR Studio 4.14

  • Support for new xmega instructions: DES, SPM Z+ (#7078, #6543)

  • Preprocessor bug when using nested preprocessor macros with arguments in conditionals (#6924)

  • Integer constant with underscores as assembler macro arguments caused syntax error (#6951)

Changes in 2.1.9 released with AVR Studio 4.12 SP3

  • Assembler now allows underscores (_) to be used as separators in integer constants.

Changes in 2.1.8

  • Bugfix: Using character constants (like 'a') in macro arguments now works.

  • Assembler now only prints long usage text if -h option given.

Changes in 2.1.7 released with AVR Studio 4.12 SP2

  • Bugfix: List file, if specified, was closed twice (no visible effect for users).

Changes in 2.1.5 released with AVR Studio 4.12 SP1

  • Bugfix: Bug causing '.if defined' to fail if used in assembler macros. See also this known issue.

  • Numerous errors in the partdef.inc include files have been fixed.

Changes in 2.1.4

  • Bugfix: .if defined and .ifdef worked differently when forward referenced symbols were involved.

  • Bugfix: Use of forward referenced symbols in .equ/.set directives.

Changes in 2.1.3

  • Minor bugfix: Incomprehensible error message if undefined preprocessor macro used in assembler macro.

Changes in 2.1.2 released with AVR Studio 4.12

  • Preprocessor: Concatenation (##) and stringification (#) operators implemented.

  • Assembler: ANSI C style string concatenation.

  • Assembler: Added conditional operator ('?') in expressions (Same as in C, e.g., a > b? a : b)

  • Assembler: Produce extended object format when source files have more than 64k lines, to enable debugging of such files (see -f command-line option)

  • The #pragma overlap directive has been enhanced to be better capable of differentiating handling in different sections of a source file. The .overlap and .nooverlap directives are added to allow selectively overlapping a section of code/data.

  • Problems with preprocessor macros and C-style comments in assembler macro calls fixed

  • Problems with mixture of preprocessor (#if) and assembler (.if) conditionals fixed

  • Preprocessor macros now evaluated when assembler macro is defined, not when it is called.

  • Conditionals may now span macro begin or end directives.

Changes in 2.0.31 released with AVR Studio 4.11 SP3

  • Fixed: Mis-parsing of ',' and '\'' character constant in preprocessor, causing syntax errors.

  • Fixed: Cryptic "internal error" messages when attempting to do assembler conditionals on forward-referenced symbols (see known issue).

  • Fixed: Assembler producing "empty" (containing header only) output files when the source file could not be opened.

Changes in 2.0.30 released with AVR Studio 4.11 SP2

  • Fixed: Off-by-one error caused relative branches (rjmp/rcall) to be reported out of range for exactly one target location in devices with 8kB flash.

Changes in 2.0.29 released with AVR Studio 4.11 SP1

  • Fixed error when attempting to include files by absolute pathname

  • Allow form-feeds in assembler source (treat as whitespace).

Changes in 2.00 RELEASE (2.0.28) released with AVR Studio 4.11

  • New include files.

  • New Pre-defined macros

  • -FD/-FT options control __DATE__/__TIME__ pre-defined macro format.

  • A lot of bugs reported by beta testers are fixed for the final release. These include

    • Improved error reporting. I.e., less "Syntax error: Unexpected FOOBAR" messages in common error situations.

    • Fixed binary number case sensitivity bug - i.e., 0b and 0B are now equivalent.

    • Fixed bug in macro argument propagation in nested macro calls.

    • Fixed incorrect #elif/.elif conditional evaluation.

    • Fixed some of bugs causing assembler to crash or hang when incorrect programs were assembled.

    • Fixed off-by-one error in reference to include statement line number.

    • Missing .warning assembler directive implemented.

    • Default byte operand range check is now sane.

    • Delete all output files (.hex,.obj,.lst,.map) on failure.

    • Warn about empty source files (no code or data), produce no output if source file is empty.

This following identifies the changes made in the latest AVRASM2 beta releases.

Changes in BETA5:

  • Preprocessor conditionals in assembler macros now work

  • Command-line options and pragmas for byte operand out of range warnings.

  • List files: Code inside false conditionals is not listed.

  • Bugfix: Incorrect filename in error message when error in nested include files.

  • Bugfix: Assembler directives like .dw didn't work in preprocessor

  • Bugfix: Use of preprocessor macros in assembler macros caused @x parameters to
    be incorrectly evaluated

Changes in BETA4:

  • Allow .set and .def directives in macros

  • .exit directive fixed

Changes between Assembler 1 and Assembler 2

C-style preprocessor

AVRASM2 features directives modeled after the C preprocessor; see AVR Assembler 2 Preprocessor. Preprocessor symbols may be defined and undefined from the command line.

Tightened syntax

The assembler syntax has been tightened up a bit, assembler keywords (instructions, registers, built-in functions) can no longer be used as user-defined symbols (labels, names in .def/.equ/.set directives). Even though this breaks some existing code, it should help avoiding some nasty bugs and generally cause programs to become more readable.

Unsupported instructions

The use of unsupported instructions will now generate an assembler error, not a warning. This behaviour may be changed in the Studio assembler settings window, and with the command-line option -W+iw.

New assembler directives

.undef symbol

Undefines a register definition created with the .def directive. Use this to avoid “already defined by the .DEF directive” warnings.

.dd expression[, expression ...]
.dq expression[, expression ...]

These directives are similar to the .dw directive, except they are used to define doublewords (32-bit) and quadwords (64-bit), respectively. The byte and word ordering is strictly little-endian.

.warning "<message>"

Print a warning message.

Improved expression evaluation

Constant expressions can be integer or floating point, and follow the C rules for operator precedence and type propagation. Symbols and instruction operands are always integer, a suitable conversion function should be used to convert before assignment (eg, int(), q7() described below).

Implicit float->int conversion cause a warning and the fractional part is discarded. Both integers and floating point numbers have 64-bit internal representation.

AVRASM2 supports the same operators as AVRASM, and additionally % (modulo/remainder).

In addition to the functions supported by AVRASM, the following new functions are supported by AVRASM2:

int()

Truncates a floating point expression to integer (ie discards fractional part)

frac()

Extracts fractional part of a floating point expression (ie discards integer part).

q7()

Converts a fractional floating point expression to a form suitable for the FMUL/FMULS/FMULSU instructions. (sign + 7-bit fraction)

q15()

Converts a fractional floating point to the form returned by the FMUL/FMULS/FMULSY instructions (sign + 15-bit fraction).

abs()

Returns the absolute value of a constant expression.

Built-in “known place” for included files

Unlike AVRASM1, when AVRASM2 is installed as part of an AVR Studio installation, it will know where the Appnotes (include) directory is, and doesn’t need to be told this via a command line option like

-I “C:\Program Files\Atmel\AVR Tools\AvrAssembler2\Appnotes”

This is convenient when the assembler is invoked as a standalone program from the command line.

Motorola hex for large files

A long-standing bug in AVRASM is fixed in AVRASM2: Motorola hex (S-record) output format is now implemented for addresses above the 64kB limit, using S2 data records when segment size exceeds 64 k bytes.

Macro improvements

  • The number of parameters to an assembler macro is unlimited in AVRASM2 (max 10 in AVRASM)

  • Nested macro calls (i.e., one macro calling another) is allowed in AVRASM2 - overuse of this feature is not recommended, however.


AVR Assembler 2 Syntax

The basic AVRASM syntax is described here, AVRASM2 is compatible with this with exceptions as noted below.

Keywords
Preprocessor directives
Comments
Line continuation
Strings and character constants
Multiple instructions per line
Operands

Keywords

Unlike AVRASM, predefined identifiers (keywords) are reserved and cannot be redefined. The keywords include all instructions, registers R0-R31 and X, Y, Z, and all functions.

Assembler keywords are recognized regardless of case, unless the case-sensitive option is used, in which case the keywords are lower case (i.e., "add" is reserved, "ADD" is not).

Example

The following nonsensical and rather obfuscated program assembles without errors with AVRASM, but is incorrect with AVRASM2.

.equ add = 2 ; 'add' is a keyword (instruction)
.def r1 = r16 ; 'r1' is a keyword (register)
.def r0 = r31 ; 'r0' is a keyword (register)
.def r16 = r24 ; 'r16' is a keyword (register)
.def add = r2 ; 'add' is a keyword - again (instruction)
.def mov = r29 ; 'mov' is a keyword (instruction)

mov: cpi r16,100 ; 'mov' is a keyword - again (instruction)
mov mov,mov ; This gets interesting... :)
ldi mov,mov ; ... not to mention this!
mov r1,add ; Which definition of 'add' is used here?
mov r0,r1 ; Things are not what they seem!
rjmp mov ; Now what...?

Preprocessor directives

AVRASM2 considers all lines starting with a '#' as the first non-space character a preprocessor directive.

Comments

In addition to the classic assembler comments starting with ';', AVRASM2 recognizes C-style comments. The following comment styles are recognized:

; The rest of the line is a comment (classic assembler comment)
// Like ';', the rest of the line is a comment
/* Block comment; the enclosed text is a comment, may span multiple lines.
This style of comments cannot be nested. */

Line continuation

Like in C, source lines can be continued by means of having a backslash (\) as the last character of a line. This is particularly useful when defining long preprocessor macros, and for long .db directives.

Example

.db 0, 1, "This is a long string", '\n', 0, 2, \
"Here is another one", '\n', 0, 3, 0

Integer constants

In addition to the integer syntax supported with AVRASM, AVRASM2 allows underscores (_) to be used as separators for increased readability. Underscores may be located anywhere in the number except as the first character or inside the radix specifier. Example: 0b1100_1010 and 0b_11_00_10_10_ are both legal, while _0b11001010 and 0_b11001010 are not.

Strings and character constants

AVRASM2 understands strings and characters in the same manner as AVRASM, except from the use of escape sequences, which is not supported by AVRASM.

A string enclosed in double quotes (") can only be used in conjunction with the .db directive and the .message/.warning/.error directives. The string is taken literally, no escape sequences are recognized, and it is not NUL-terminated.

Quoted strings may be concatenated according to the ANSI C convention, i.e., "This is a " "long string" is equivalent to "This is a long string".This may be combined with line continuation to form long strings spanning multiple source lines.

Character constants are enclosed in single quotes ('), and can be used anywhere an integer expression is allowed. The following C-style escape sequences are recognized, with the same meaning as in C:

Escape sequence | Meaning
\n | Newline (ASCII LF 0x0a)
\r | Carriage return (ASCII CR 0x0d)
\a | Alert bell (ASCII BEL 0x07)
\b | Backspace (ASCII BS 0x08)
\f | Form feed (ASCII FF 0x0c)
\t | Horizontal tab (ASCII HT 0x09)
\v | Vertical tab (ASCII VT 0x0b)
\\ | Backslash
\0 | Null character (ASCII NUL)

\ooo (ooo = octal number) and \xhh (hh = hex number) are also recognized.

Examples
.db "Hello\n" // is equivalent to:
.db 'H', 'e', 'l', 'l', 'o', '\\', 'n'
.db '\0', '\177', '\xff'

To create the equivalent to the C-string "Hello, world\n", do as follows:

.db "Hello, world", '\n', 0

Multiple instructions per line

AVRASM2 allows multiple instructions and directives per line, but its use is not recommended. It is needed to support expansion of multiline preprocessor macros.

Operands

In addition to the integer operands supported by AVRASM, AVRASM2 has limited support for floating point constant expressions. All operands are described here.


AVR Assembler 2 Preprocessor

Introduction
Preprocessor directives
Operators
Pre-defined macros

Introduction

The AVRASM2 preprocessor is modeled after the C preprocessor, with some exceptions:

  • It recognizes all integer formats used by AVRASM2, i.e., $abcd and 0b011001 are recognized as valid integers by the preprocessor and can be used in expressions in #if directives.

  • '.' and '@' are allowed in identifiers. '.' is required to allow preprocessor directives like '.dw' to be used in preprocessor macros, '@' is required to handle assembler macro arguments correctly.

  • It recognizes assembler-style comment delimiters (';') as well as C-style comments. Using ';' as a comment delimiter is in conflict with the C use of ';', and it is therefore not recommended to use assembler-style comments in conjunction with preprocessor directives.

  • The #line directive is not implemented

  • Variadic macros (i.e., macros with variable number of arguments) are not implemented.

  • The #warning and #message directives are not specified in the ANSI C standard.

Preprocessor directives

#define
#elif
#else
#endif
#error

#if
#ifdef
#ifndef
#include
#message

#pragma
#undef
#warning
# (empty directive)

Operators:

# (stringification
## (concatenation)

#define

Syntax

  1. #define name [value]

  2. #define name(arg, ...) [value]

Description

Define a preprocessor macro. There are two forms of macros, (1) object-like macros that basically define a constant, and (2) function-like macros that do parameter substitution.

value may be any string, it is not evaluated until the macro is expanded (used). If value is not specified, it is set to 1.

Form (1) macros may be defined from the command line, using the -D option.

When form (2) is used, the macro must be called with the same number of arguments it is defined with. Any occurrences of arg in value will be replaced with the corresponding arg when the macro is called. Note that the left parenthesis must appear immediately after name (no spaces between), otherwise it will be interpreted as part of the value of a form (1) macro.

Examples

Note that the placement of the first '(' is very significant in the examples below.

  1. #define EIGHT (1 << 3)

  2. #define SQR(X) ((X)*(X))

#undef

Syntax

#undef name

Description

Undefine macro name previously defined with a #define directive. If name is not previously defined, the .undef directive is silently ignored, this behaviour is in accordance with the ANSI C standard. Macros may also be undefined from the command line using the -U option.

#ifdef

Syntax

#ifdef name

Description

All following lines until the corresponding #endif, #else, or #elif are conditionally assembled if name is previously #defined. Shorthand for #if defined(name)

Example

#ifdef FOO
// do something
#endif

#ifndef

Syntax

#ifndef name

Description

The opposite of #ifdef: All following lines until the corresponding #endif, #else, or #elif are conditionally assembled if name is not #defined. Shorthand for #if !defined(name)

#if
#elif

Syntax

#if condition

#elif condition

Description

All following lines until the corresponding #endif, #else, or #elif are conditionally assembled if condition is true (not equal to 0). condition may be any integer expression, including preprocessor macros which are expanded. The preprocessor recognizes the special operator defined(name) that returns 1 if name is #defined and 0 otherwise. Any un#defined symbols used in condition are silently evaluated to 0.

Conditionals may be nested to arbitrary depth.

#elif evaluates condition in the same manner as #if, except that it is only evaluated if no previous branch of a compound #if .. #elif sequence has been evaluated to true.

Examples

#if 0
// code here is never included
#endif

#if defined(__ATmega48__) || defined(__ATmega88__)
// code specific for these devices
#elif defined (__ATmega169__)
// code specific for ATmega169
#endif // device specific code

#else

Syntax

#else

Description

All following lines until the corresponding #endif are conditionally assembled if no previous branch in a compound #if ... #elif ... sequence has been evaluated to true.

Example

#if defined(__ATmega48__) || defined(__ATmega88__)
// code specific for these parts
#elif defined (__ATmega169__)
// code specific for ATmega169
#else
#error "Unsupported part:" __PART_NAME__
#endif // part specific code

#endif

Syntax

#endif

Description

Terminates a conditional block initiated with an #if, #ifdef, or #ifndef directive.

#error
#warning
#message

Syntax

#error tokens

#warning tokens

#message tokens

Description

#error emits tokens to standard error, and increments the assembler error counter, hereby preventing the program from being successfully assembled. #error is specified in the ANSI C standard.

#warning emits tokens to standard error, and increments the assembler warning counter. #warning is not specified in the ANSI C standard, but is commonly implemented in preprocessors such as the GNU C preprocessor.

#message emits tokens to standard output, and does not affect assembler error or warning counters. #message is not specified in the ANSI C standard.

For all directives, the output will include file name and line number, like normal error and warning messages.

tokens is a sequence of preprocessor tokens. Preprocessor macros are expanded except if appearing inside quoted strings (").

Example

#error "Unsupported part:" __PART_NAME__

#include

Syntax

  1. #include "file"

  2. #include <file>

Description

Include a file. The two forms differ in that (1) searches the current working directory first, and is functionally equivalent with the assembler .include directive. (2) does not search the current working directory unless explicitly specifying it with an "." entry in the include paht. Both forms will search a built-in known place after any explicitly specified path, this is the location for the partdef.inc include files supplied with the assembler.

It is strongly discouraged to use absolute pathnames in #include directives, as this makes it difficult to move projects between different directories/computers. Use the -I command-line option to specify the include path, or set ut up in AVR Studio - Project - Assembler Options.

Examples

#include <m48def.inc>

#include "mydefs.inc"

#pragma, general-purpose

Syntax

  1. #pragma warning range byte option

  2. #pragma overlap option

  3. #pragma error instruction

  4. #pragma warning instruction

Description

  1. The assembler evaluates constant integer expressions as 64-bit signed integers internally. When such expressions are used as immediate operands, they must be truncated to the number of bits required by the instructions. For most operands, an out-of -range value will cause an "operand out of range" error message. However, the immediate byte operands for the ldi, cpi, ori, andi, subi, sbci instructions have several possible interpretations that are affected by this option.
    option     = integer The immediate operand is evaluated as an integer, and if its value is outside the range [-128 ... 255] a warning is given. The assembler doesn't know if the users intends an integer operand to be signed or unsigned, hence it allows any signed or unsigned value that fits into a byte.
    option     = overflow (default): The immediate operand is basically evaluated as an unsigned byte, and any sign extension bits are ignored. This option is particularly suitable when dealing with bit masks, when the integer interpretation would cause lots of warnings, like ldi r16, ~((1 << 7) | (1 << 3))
    option     = none Disables all out-of-range warnings for byte operands. Not recommended.

  2. If different sections of code are mapped to overlapping memory locations using the .org directive, an error message is normally issued. This options modifies that behaviour as follows:
    option     = ignore Ignores overlap conditions altogether; no errors, no warnings. Not recommended.
    option     = warning Produce warnings when overlaps are detected.
    option     = error Consider overlaps as error condition; this is the default and recommended setting.
    option     = default Revert to default handling - error or whatever is specified with the -O command line option.

    The assembler maintains two settings for overlap handling: The     default setting that is set up by the -O command-line option, and the effective setting, that only can be modified with this #pragma. The two settings are equal upon assembler invocation, this #pragma changes the effective setting from the line it is invoked and until the line it is changed by another invocation of this pragma. Hence, this pragma covers source line ranges and not address ranges.

    See also: .overlap directive.

  3. Causes use of instructions that are unsupported on the specified device to cause an assembler error (default behaviour)

  4. Causes use of instructions that are unsupported on the specified device to cause an assembler warning.

See also

  1. Command-line option -W.

  2. Command-line option -O.

#pragma, AVR part related

Syntax

  1. #pragma AVRPART ADMIN PART_NAME string

  2. #pragma AVRPART CORE CORE_VERSION version-string

  3. #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED mnemonic[ operand[,operand] ][:...]

  4. #pragma AVRPART CORE NEW_INSTRUCTIONS mnemonic[ operand[,operand]][:...]

  5. #pragma AVRPART MEMORY PROG_FLASH size

  6. #pragma AVRPART MEMORY EEPROM size

  7. #pragma AVRPART MEMORY INT_SRAM SIZE size

  8. #pragma AVRPART MEMORY INT_SRAM START_ADDR address

  9. #pragma partinclude num

Description

These directives are used to specify various part-specific properties, and are normally used in the part definition include files (partdef.inc). Normally, there is no reason to use these pragmas directly in user programs.

Preprocessor macros are not allowed in pragmas. Expressions are not allowed for the numeric arguments, must be pure numbers in decimal, hex, octal, or binary format. String arguments must not be quoted. The pragmas specify the following part-specific properties:

  1. The part name, e.g., ATmega8

  2. The AVR Core version. This defines the basic instruction set supported. Allowed core versions are currently V0, V0E, V1, V2, and V2E.

  3. Colon-separated list of instructions not supported by this part, relative to the core version.

  4. Colon-separated list of additional instructions supported by this part, relative to the core version.

  5. FLASH program memory size, in bytes.

  6. EEPROM memory size, in bytes.

  7. SRAM memory size, in bytes.

  8. SRAM memory start address. 0x60 for basic AVR parts, 0x100 or more for parts with extended I/O.

  9. For AVRASM1 compatibility. Default value: 0. If set to 1, it will cause the .device directive to include a file called device.h that is expected to contain the #pragmas described above. This enables partdef.inc files designed for AVRASM1 (containing a .device directive but no part-describing #pragmas) to be used with AVRASM2. This property can also be set using the -p command-line option, and is implicitly set when using the -1 command-line option.

Examples

Please note that the combination of these examples does not describe a real AVR part!

  1. #pragma AVRPART ADMIN PART_NAME ATmega32

  2. #pragma AVRPART CORE CORE_VERSION V2

  3. #pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED movw:break:lpm rd,z

  4. #pragma AVRPART CORE NEW_INSTRUCTIONS lpm rd,z+

  5. #pragma AVRPART MEMORY PROG_FLASH 131072

  6. #pragma AVRPART MEMORY EEPROM 4096

  7. #pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60

  8. #pragma AVRPART MEMORY INT_SRAM SIZE 4096

# (empty directive)

Syntax

#

Description

Unsurprisingly, this directive does exactly nothing. The only reason it exists is that it is required by the ANSI C standard.

Operators

Stringification (#)

The stringification operators makes a quoted string token of a parameter to a function-type macro

Example

#define MY_IDENT(X) .db #X, '\n', 0

When called like this

MY_IDENT(FooFirmwareRev1)

will expand to

.db "FooFirmwareRev1", '\n', 0

Notes

  1. Stringification can only be used with parameters to function-type macros

  2. The parameter's value will be used literally, i.e. it will not be expanded before stringification.

Concatenation (##)

The concatenation operator concatenates two preprocessor tokens, forming a new token. It is most useful when at least one of the tokens are a parameter to a function-type macro.

Example

#define FOOBAR subi

  1. #define IMMED(X) X##i

  2. #define SUBI(X,Y) X ## Y

When the IMMED and SUBI macros are called like this:

  1. IMMED(ld) r16,1

  2. SUBI(FOO,BAR) r16,1

they will be expanded to

  1. ldi r16,0x1

  2. subi r16,0x1

Notes

  1. The concatenation operator cannot appear first or last in a macro expansion

  2. When used on a function-type macro argument, the argument will be used literally, i.e., it will not be expanded before concatenation.

  3. The token formed by the concatenation will be subject to further expansion. In example 2 above, the parameters FOO and BAR are first concatenated to FOOBAR, then FOOBAR is expanded to subi.

Pre-defined macros

The preprocessor has a number of pre-defined macros. All have names starting and ending with two underscores (__). To avoid conflicts, user-defined macros should not use this naming convention.

Pre-defined macros are either built-in, or they are set by the #pragma directive, as indicated in the table.

Name | Type | Set by | Description
__AVRASM_VERSION__ | Integer | Built-in | Assembler version, encoded as (1000*major + minor)
__CORE_VERSION__ | String | #pragma | AVR core version.
__DATE__ | String | built-in | Build date. Format: "Jun 28 2004", see -FD command-line option.
__TIME__ | String | built-in | Build time. Format: "HH:MM:SS". see -FT command-line option
__CENTURY__ | Integer | built-in | Build time century (typically 20)
__YEAR__ | Integer | built-in | Build time year, less century (0-99)
__MONTH__ | Integer | built-in | Build time month (1-12)
__DAY__ | Integer | built-in | Build time day (1-31)
__HOUR__ | Integer | built-in | Build time hour (0-23)
__MINUTE__ | Integer | built-in | Build time minute (0-59)
__SECOND__ | Integer | built-in | Build time second (0-59)
__FILE__ | String | built-in | Source file name.
__LINE__ | Integer | built-in | Current line number in source file.
__PART_NAME__ | String | #pragma | AVR part name.
__partname__ | Integer | #pragma | partname corresponds to the value of __PART_NAME__. Example: #ifdef __ATmega8__
__CORE_coreversion__ | Integer | #pragma | coreversion corresponds to the value of __CORE_VERSION__. Example: #ifdef __CORE_V2__


AVR Assembler 2 Command Line Options

Like AVRASM, AVRASM2 may be used as a stand-alone program from the command line. The AVRASM2 command-line invocation syntax is shown below. Many options are the same as in AVRASM, new/changed AVRASM2 options are shown in bold and described below.

usage: avrasm2.exe [options] file.asm

Options:
-f [O|M|I|G|-] output file format:
  -fO Debug info for simulation in AVR Studio (default)
         -fO1 | -fO2 - force format version 1 or 2 (default: auto)
  -fM Motorola hex
  -fI Intel hex
  -fG Generic hex format
  -f- No output file
-o ofile   Put output in 'ofile'.
-d dfile   Generate debug info for simulation in AVR Studio in 'dfile'.
Can only be used with the -f [M|I|G] option.
-l lfile   Generate listing in 'lfile'
-m mfile   Generate map in 'mfile'
-e efile   Place EEPROM contents in 'efile'
-w         Relative jumps are allowed to wrap for program ROM
up to 4k words in size [ignored]
-C ver     Specify AVR core version
-c         Case sensitive
-1/-2      Turn on/off AVR Assembler version 1 compatibility.
-p1|0      Set/unset AVRASM1 implicit .device include (also set by -1)
-I dir     Preprocessor: Add 'dir' to include search path
-i file    Preprocessor: Explicitly pre-include file
-D name[=value] Preprocessor: Define symbol. If =value is
omitted, it is set to 1.
-U name    Preprocessor: Undefine symbol.
-v verbosity [0-9][s]:
-vs Include target resource usage statistics
-vl Output low-level assembly code to stdout
-v0 Silent, only error messages printed
-v1 Error and warning messages printed
-v2 Error, warning, and  info messages printed (default)
-v3-v9 Unspecified, increasing amounts of assembler internal dumps.
-O i|w|e   Overlap report: ignore|warning|error [error]
-W-b|+bo|+bi Byte operand out of range warning disable|overflow|integer
-W+ie|+iw  Unsupported instruction error | warning
-FD|Tfmt   __DATE__ | __TIME__ format, using strftime(3) format string

-f output-file-format

Supported formats are generic/Intel/Motorola hex, and AVR Object files. There are two subvariants of the AVR Object file format:

  • Standard (V1) format, with 16-bit line number fields, supporting source files with up to 65534 lines.

  • Extended (V2) format, with 24-bit line number fields, supporting source files with up to ~16M lines.

By default, when output format is unspecified or specified with -fO, the assembler will select the appropriate format automatically, V1 if the file has less than 65533 lines, V2 if it has more. The -fO1 and -fO2 options may be used to force V1 or V2 output file format regardless of number of lines.

If V1 file format is used with source files with more than 65534 lines, the assembler will issue a warning, and the lines above 65534 cannot be debugged with AVR Studio. On the other hand, the V2 format is not recognized at all by AVR Studio versions prior to 4.12.

For all normal assembler projects, the default option should be safe. The extended format is primarily intended for machine-generated assembly files.

-w

Wrap relative jumps. This option is obsoleted, because AVRASM2 automatically determines when to wrap relative jumps, based on program memory size. The option is recognized but ignored.

-C core-version

Specify AVR Core version. The core version is normally specified in part definition files (partdef.inc), this option is intended for testing of the assembler, and generally not useful for end-users.

-c

Causes the assembler to become entirely case sensitive. Preprocessor directives and macros are always case sensitive. Warning: Setting this option will break many existing projects.

-1
-2

Enable and disable AVRASM1 compatibility mode. This mode is disabled (-2) by default. The compatibility mode will permit certain constructs otherwise considered errors, reducing the risk of breaking existing projects. It also affects the built-in include path, causing the assembler to look for device definition include files (devicedef.inc) for Assembler 1 in C:\Atmel\AVR Tools\AvrAssembler\Appnotes instead of the new Assembler 2 files in C:\Atmel\AVR Tools\AvrAssembler2\Appnotes (see also XML Converter). Note that recent devices may not be supported for Assembler 1.

-I directory

Add directory to the include file search path. This affects both the preprocessor #include directive and the assembler .include directive.

Multiple -I directives may be given. directories are searched in the order specified.

-i file

Include a file. #include “file” directive is processed before the first source code line is processed. Multiple –i directives may be used and will be processed in order.

-D name[=value]
-U name

Define and undefine a preprocessor macro, respectively. Note that function-type preprocessor macros may not be defined from the command line. If -D is given no value, it is set to 1.

-vs

Print use statistics for register, instruction and memory on standard output. By default, only the memory statistic is printed. Note: The full statistics will always be printed to the list file, if one is specified.

-vl

This will print the raw instructions emitted to standard output, after all symbolic info is replaced. Mainly for assembler debugging purposes.

-v0

Print error messages only, warning and info messages are suppressed.

-v1

Print error and warning messages only, info messages are suppressed.

-v2

Print error, warning, and info messages. This is the default behaviour.

-v3 ... -v9

Print increasing amounts of assembler internal status dump. Mostly used for assembler debugging.

-O i|w|e

If different sections of code are mapped to overlapping memory locations using the .org directive, an error message is normally issued.

This option allows setting this condition to cause an error (-Oe, default), a warning (-Ow) or be completely ignored (-Oi). Not recommended for normal programs.

This may also be set by #pragma overlap directive.

-W-b |-W+bo | -W+bi

-b, +bo, and +bi correspond to no no warning, warning when overflow, and warning when integer value out of range, respectively. This may also be set by #pragma warning range.

-W+ie|+iw

+ie and +iw selects if use of unsupported instructions gives error or warning, respectively. The default is to give an error. Corresponds to #pragma error instruction / pragma warning instruction, respectively.

-FDformat
-FTformat

Specify the format of the __DATE__ and __TIME__ predefined macros, respectively. The format string is passed directly to the strftime(3) C library function. The __DATE__ and __TIME__ preprocessor macros will always be string tokens, i.e., their values will appear in double quotes.

The default formats are "%b %d %Y" and "%H:%M:%S", respectively.

Example: To specify ISO format for __DATE__, specify -FD"%Y-%m-%d" See note below

These formats may only be specified at the command line, there are no corresponding #pragma directives.

Important note: The Windows command interpreter (cmd.exe or command.com) may interpret a character sequence starting and ending with a '%' character as an environment variable to be expanded even when it is quoted. This may cause the date/time format strings to be changed by the command interpreter and not work as expected. A workaround that will work in many cases is to use double '%' characters to specify the format directives, e.g., -FD"%%Y-%%m-%%d" for the example above. The exact behaviour of the command interpreter seems to be inconsistent and vary depending on a number of circumstances, for one, it is different in batch and interactive mode. The effect of the format directives should be tested. It is recommended to put the following line in the source file for testing this:

#message "__DATE__ =" __DATE__ "__TIME__ =" __TIME__

This will print the value of the date and time macros when the program is assembled, making verification easy (see #message directive documentation).

An alternative syntax for the format specification may be considered in future AVRASM2 versions to avoid this problem.

Some relevant strftime() format specifiers (see strftime(3) manual page for full details):

  • %Y - Year, 4 digits

  • %y - Year, 2 digits

  • %m - Month number (01-12)

  • %b - Abbreviated month name

  • %B - Full month name

  • %d - Day number in month (01-31)

  • %a - Abbreviated weekday name

  • %A - Full weekday name

  • %H - Hour, 24-hour clock (00-23)

  • %I - Hour, 12-hour clock (01-12)

  • %p - "AM" or "PM" for 12-hour clock

  • %M - Minute (00-59)

  • %S - Second (00-59)


AVR Assembler 2 - Known Issues

See also: Common Assembler Project Issues.

The following AVRASM2 bugs/issues are known at the time of release. Please note that the AVRASM1 known issues do not apply to AVRASM2. and vice versa.

Line continuation doesn't work in macro calls
Missing newline at end of file
Increment/decrement operators
Forward references in conditionals
Error messages
defined incorrectly treated as assembler keyword
Preprocessor issues

Issue #4146: Line continuation doesn't work in macro calls

The following program illustrates this issue.

.macro m
ldi @0, @1
.endm
m r16,\
0

This is not a problem with preprocessor macros (#define).

Missing newline at end of file

AVRASM2 has some issues if the last line in a source file is missing a newline: Error messages may refer to wrong filename/line number if the error is in the last line of a included files, and in some cases syntax errors may result. Beware that the AVR Studio editor will not append a missing newline at the end of a source file automatically.

Increment/decrement operators

Increment/decrement operators (++/--) are recognized by the assembler and may cause surprises, e.g. symbol--1 will cause a syntax error, write symbol - -1 if that is what is intended. This behaviour is consistent with C compilers. The ++/-- operators are not useful in the current assembler, but are reserved for future use.

Forward references in conditionals

Using a forward reference in an assembler conditional may cause surprises, and in some cases is not allowed. Example:

.org LARGEBOOTSTART
; the following sets up RAMPZ:Z to point to a FLASH data object, typically
; for use with ELPM.
        ldi ZL, low (cmdtable * 2)
        ldi ZH, high (cmdtable * 2)
.if ((cmdtable * 2) > 65535)
        ldi r16, 1
        sts RAMPZ, r16
.endif
        ; more code follows here
cmdtable: .db "foo", 0x0

The reason for this is that the outcome of the conditional will influence the value of the forward referenced label, which in turn may affect the outcome of the conditional, and so on.

The following is allowed:

.ifdef FOO
nop ; some code here
.endif
rjmp label
; more code here
.equ FOO = 100
label:
nop

In this example FOO is not defined at the point it is used in a conditional. The use of .ifdef in this situation is allowed, and the conditional is false. However, the pattern shown above is not recommended because the programmer's intention is not clear. The form is intended to allow common constructs like this:

; Define FOO if it is not already defined.
.ifndef FOO
.equ FOO = 0x100
.endif

Up to and including AVRASM 2.0.30, these situations were not always properly detected, causing incomprehensible error messages. Starting with 2.0.31, explicit error messages are given.

Note that with preprocessor conditionals (#if/#ifdef), the situation is always well-defined, preprocessor symbols are always undefined until the definition is seen. and this kind of error will never occur.

Error messages

Sometimes error messages may be hard to understand. Typically, a simple typo in some instances may produce error messages like this:

myfile.asm(30): error: syntax error, unexpected FOO

where FOO represents some incomprehensible gibberish. The referenced filename/line number is correct, however.

defined incorrectly treated as an assembler keyword

The keyword defined is recognized in all contexts, it should only be recognized in conditionals. This prevents defined to be used as a user symbol like a label, etc. On the other hand, it allows for constructs like '.dw foo = defined(bar)' which it shouldn't. Note that the preprocessor and assembler have separate implementations of defined. The exact behaviour of defined currently (from 2.1.5) is:

  • The preprocessor 'defined' keyword only relates to symbols defined with #define, and correctly does this only in preprocessor conditionals (#if/#elif).

  • In all remaining code, the assembler's notion of defined is used, the correct behaviour would be to only recognize it in assembler conditionals (.if/.elif).

Preprocessor issues

  • The preprocessor will not detect invalid preprocessor directives inside a false conditional. This may lead to surprises with typos like this:
    #if __ATmega8__
    //...
    #elseif __ATmega16__ //     WRONG, the correct directive is #elif
    // This will go undetected if __ATmega8__ is false
    //...
    #else
    // when __ATmega8__ is false this section will be assembled even if
    // __ATmega16__ is true.
    #endif
    It is debatable if this is a bug, the behaviour is consistent with the C preprocessor.

  • Issue #3361: The preprocessor incorrectly allows additional text after directives, which may cause surprises, e.g.,
    #endif #endif
    will be interpreted as a single #endif directive, without any error or warning message.

  • Issue #4741: Assembler conditionals in preprocessor macros don't work
    Use of the macro defined below will result in different syntax error messages, depending on the value of the conditional val (true or false)

    #define TEST \
    .IF val \
    .DW 0 \
    .ELSE \
    .DW 1 \
    .ENDIF

    The reason for this is that assembler conditionals must appear on a separate line, and a preprocessor macro like the above is concatenated into a single line.


XML Converter

  • Location and invocation

  • Example: Create assembler include file

  • Example: Create header files for IAR Compiler

  • Example: Create header files for GCC

  • Changelog

Introduction

The XML Converter is a separate command-line tool used to produce assembler include files and C header files from the part description files (XML) used by AVR Studio. Notice: The XML converter can not be used to produce assembler include for xmega devices.

All assembler include files for AVR Assembler 2 in the AVR Studio distribution are produced using this tool. The tool is also capable of producing C header files.

The XML converter program is presently not available from the AVR Studio GUI, and must be invoked from the command line.

Location and invocation

The following assumes AVR Studio is installed in the default directory
C:\Program Files\Atmel\AVR Tools. If that is not the case, adjust the following accordingly.

The XML converter is located here:

C:\Program Files\Atmel\AVR Tools\AvrStudio4\xmlconvert.exe

For convenient access, the XML converter directory should be included in PATH, this can be done from Control panel -> System Properties, or from the command line with the following command:

PATH = %PATH%;"C:\Program Files\Atmel\AVR Tools\AvrStudio4"

Assuming this is in place, the XML converter can be accessed by typing xmlconvert from the command prompt. When invoked without arguments, xmlconvert print a usage message:

xmlconvert: No source file specified
Usage: xmlconvert [-f output-format] [-o outdir] [-1nbclV] infile ...
Output formats: a[vrasm] | i[ar] | c[c] (generic c)
Options:
-1  = Don't generate AVRASM2 #pragma's
-n  = Don't warn about bad names
-b  = use DISPLAY_BITS attribute to limit bit definitions
-c  = Add some definitions for compatibility with old files
-l  = Produce linker file (IAR only)
-q  = Allow linked register quadruple (32-bit)
-V  = print xmlconvert version number

The AVR part description files reside in C:\Program Files\Atmel\AVR Tools\Partdescriptionfiles. There is one file per part. The use is simplest explained by some examples:

Create assembler include file for mega128

xmlconvert -c -o c:\Work\Tmp "C:\Program Files\Atmel\AVR Tools\Partdescriptionfiles\ATmega128.xml"

This creates an assembler include file for mega128 in the output directory C:\Work\Tmp. If the -o option is omitted, the output file(s) will be located in the same directory as the input file.

Note: The -c option should always be used, if the created files are to be compatible with existing files.

The output file from this command will be C:\Work\Tmp\m128def.inc.

Create header and link files for all devices for the IAR C compiler

cd "C:\Program Files\Atmel\AVR Tools\Partdescriptionfiles"
xmlconvert -c -n -fiar -l -o C:\Work\tmp *.xml

When using multiple input files it is recommended to cd to the source directory first. The -fiar option requests IAR output files, the -l option requests linker file creation, the -n option suppresses some warning messages.

Note: the linker file facility is somewhat experimental and the resulting file may require editing before being usable, depending on device. Please consult the IAR manuals for details about these files.

File name conventions

The XML part description files are always named devicename.xml. The following conventions are used for producing assembler file names for various AVR device families. nnn refers to the number section of a device name (e.g., 2313 in ATtiny2313).

  • Classic AVR devices: AT90Snnn -> nnndef.inc. Example: AT90S8515 -> 8515def.inc

  • Tiny AVR devices: ATtinynnn -> tnnnndef.inc. Example: ATtiny13 -> tn13def.inc

  • Mega AVR devices: ATmegannn -> mnnndef.inc. Example: ATmega644 -> m644def.inc

  • AVR CAN devices: AT90CANnnn -> cannnndef.inc. Example: AT90CAN128 -> can128def.inc

  • AVR PWM devices: AT90PWMnnn -> pwmnnndef.inc. Example: AT90PWM3 -> pwm3def.inc

When producing header files for the C compilers XML converter attempts to follow the conventions used by the respective compiler manufacturers. For instance, IAR will call the ATmega128 header file iom128.h. The XML converter obeys these conventions as far as they are known/documented.

If the 'generic C' format is selected, the header files are simply named device.h, e.g., ATmega128.h.

Changelog

Version 2.30, released with AVR Studio 4.15

  • GCC support removed, as it has been unmaintained, and other tools exists to make header files for WinAVR. (#8158)

  • Fixed issue with interrupt vectors for PWM devices (#8723)

Version 2.24, released with AVR Studio 4.12 SP4

  • Bug fixed: Dropped some bit definitions (Issue #4757)

Version 2.20, released with AVR Studio 4.12

  • Minor bug fixes and enhancements only.

Version 2.17, released with AVR Studio 4.11 SP1

  • Removed bogus EEADRBITS output for parts without EEPROM

  • Added support for tiny28 LowLevel interrupt vector

  • Added experimental support for 32-bit register quadruples (-q option).

  • Wrong output file name if upper/lower case mismatch in input filename.